i.MX6DL IOMUX setting

https://community.nxp.com/thread/325322

https://github.com/UDOOboard/Kernel_Unico/blob/master/arch/arm/mach-mx6/board-mx6q_sabresd.h

https://github.com/UDOOboard/Kernel_Unico/blob/master/arch/arm/mach-mx6/board-mx6dl_sabresd.h


https://github.com/UDOOboard/Kernel_Unico/blob/8a6eb060a0d968048f88d5a94510fc6db2c37939/arch/arm/plat-mxc/iomux-v3.c
https://github.com/engicam-stable/iCoreM6_linux/blob/5f94a3d5dbd4e761d9a0a021ec0d4104a41e8df8/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h#L57


For i.MX 6SoloX, the following is the source:
https://elixir.bootlin.com/u-boot/v2017.11-rc3/source/board/freescale/mx6sxsabresd/mx6sxsabresd.c
U-Boot does not have the ENET2 support. To add it follow this.
https://community.nxp.com/thread/466067
https://git.rigado.com/vesta/u-boot-imx/commit/3d3d8f5f1910ccc5659095a50c2fd4dd139ecdda
Configuration Macro: CONFIG_MX6SX
Device Tree file
https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/imx6sx-sdb.dtsi
MX6 Important Settings:
1) PLL -> Division factor and Clock enable bits for each channel
2) IOMUX_MUX
3) IOMUX_PAD
4) IOMUX_INPUT
5) PHY settings - Delay etc
6) MAC settings
7) Power IO pins etc.
8) Clock Module Enable

i.MX Linux Reference Manual
http://caxapa.ru/thumbs/905619/i.MX_Reference_Manual.pdf

Mystery Phenonmenon

Sometimes ping sometimes not and the speed is slower sometimes:

It was ethmb9.c which was inconsistent in ping that sometimes it pings and sometimes it does not ping immediately after or permanently after restarting. It was twice or thrice in ten times. And, even it pings, the speed is comparatively slow with other cases.

It was purely the distance between the setting of Speed/Duplex settings in MCR register and starting the Tx/Rx. It needs sometimes once set the mode to stabilize. So, I made the setting of MCR at starting of lan_start() and start settings at the end of it.

MasterSar

Not catch up! But, Master the source!! Write the articles and light the world with your knowledge!!!

Make ready the end user products. Autosar with CAN driver stack in all platforms demonstration.

https://www.youtube.com/watch?v=XEI9ZH3rRz8

TEXAS INSTRUMENTS EK-TM4C123GXL Tiva C Series TM4C123G LaunchPad Evaluation Kit

http://www.ti.com/lit/ug/spmu296/spmu296.pdf

CAN communication with single TIVA C Launchpad , between two CAN port

http://e2e.ti.com/support/microcontrollers/other/f/908/t/433816

CAN protocol basics

Some of the Protocols

CAN物理層のOpen Field Network
CANopen or DeviceNet
プロトコル対応品。

To try Autosar CAN communication first
Introduction to NXP AUTOSAR MCAL Software

https://www.nxp.com/video/:AUTOSAR-OnDemand-Training-Video

Tutorial about Porting Autosar to Embedded System
http://www.diva-portal.org/smash/get/diva2:648352/FULLTEXT01.pdf

Questions about AutoSAR  starter kit  on S32K144EVB
https://community.nxp.com/thread/484052

CAN Primer: Creating your own Network
https://www.keil.com/download/files/can_primer_2009sp.pdf


Introduction to UDS Part1 - UDS background
https://www.youtube.com/watch?v=lY585Yp7zeY&list=PL7RbKI2JHDnIOuom0pTQfiQaWULt3MWja&index=2

Eclipse project: Refresh policy

MCIMX6DL-SDB

Chip On Board:
https://www.nxp.com/part/MCIMX6U8DVM10AC
https://www.nxp.com/docs/en/data-sheet/IMX6SDLCEC.pdf

Quick Start Board:
https://www.nxp.com/docs/en/user-guide/SABRESDB_IMX6_QSG.pdf

Top Ten Single Board Computers

https://www.eetimes.com/document.asp?doc_id=1333687&page_number=8

Rear View camera Module

How to Install a Rear View Backup Camera | Step by Step Installation & Buying Guide
https://www.youtube.com/watch?v=Qh-crI3LAg8

Automotive Camera Module Reference Design with 1MPixel Imager, Bayer Video Output & Power over Coax
http://www.ti.com/tool/TIDA-01004


What understood?
1) Camera module just needs Video output, Power Harness, Reverse Trigger signal which is 12V.
Which triggers?
Radio triggers it once the reverse gear is made. See the operation principle of the rear view system.

2) Camera module needs to give the video output. It needs to be a separate MCU so that it does all processing within it.
Yes. But, Rear View camera or Backup camera may not an ECU. Because, it does not control anything. It just sends the video capture to the display when instructed by the Radio. But, ECU is different that it sends the control parameters to the Radio.

3) Separate displays also provided for the cars.
----

1) What does he spoke about taking the source code from vehicle?
2) Do we need to design the camera module? Or, only software? Are they provide the hardware modules needed?

3) What is the interface? Does it for regulating the power and where the camera module needs to be interfaced?

4) What is interface power and triggers? what is for dip swtich?

5) What we need to do exactly?
----

How the real view camera is interfaced and programmed in Info3L?

I remember, in INFO3 LOW, only on rear-view camera, the display is controlled by SH itself. So, that settings will be in the source code.


https://www.bosch-mobility-solutions.com/en/products-and-services/passenger-cars-and-light-commercial-vehicles/driver-assistance-systems/rear-view-system/

Operation principle of the rear view system

The camera in the vehicle’s rear becomes automatically active as soon as the reverse gear is engaged. The camera image displays the area behind the vehicle and allows the driver to determine in real time whether the path is clear. Optionally, the vehicle’s path can be shown dynamically on the camera image with the help of colored lines. These display the vehicle’s trajectory according to the current steering-wheel angle and indicate when the steering wheel must be turned.

In combination with the ultrasonic-based parking aid, for example, distances measured by the ultrasonic sensors are displayed as colored bars in the camera image. This means that all relevant information is available to the driver at a glance.

PHY access in NIOS

There is common bus for all PHY devices. But, there is facility to map maximum of two devices at the same time.

The following is wrong.
--

So, when the MDIO Address 0 Register is written with any PHY Address, corresponding PHY registers are mapped to MDIO Space 0. Similarly, when MDIO Address 1 Register is written with a PHY address, that PHY will be mapped to MDIO Space 1.

So, there should be fixed PHY address for each channel. PHY Address 0 should be written to MDIO address 0 and MDIO Space 0 should be accessed in phynios.c. Similarly, all 1 should be accessed in second channel driver.
--

Each MAC (TSE0 & TSE1) can map up to two PHY devices in either  MDIO Space 0 or MDIO Space1. The offset for MDIO Space 0 = 0x200 (Base offset in manual * 4). But, why do I need two PHYs for single mac? So, I just use MDIO Space 0 for mapping the corresponding PHY in each channel.

See below. Without any doubt, the instances share MDIO master. So, single shared MDIO bus.

http://www.inferq.com/contact-us.aspx
http://nextwebi.com/quick-inquiry.aspx

ARM Memory Attributes

fm3 mb9bf618t Ethernet driver

The speed should be TTCP -t → 9600 Mbps. TTCP -r → 10000 Mbps. Otherwise, there are some issues. Mainly the MAC_MCR should be immediately after PHY init and must be far from the next MAC register (MAC_MFFR) initialization. As per manual, 2 PHY clock cycle delay should be there after MAC_MCR initialization. Otherwise, in 20 times, there will be few times, when board is started, the Ethernet does not ping.

Unaligned access in memcpy

Do not use memcpy in Device Memory.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka15414.html

Library built with Unaligned access flag.
https://bugs.launchpad.net/gcc-arm-embedded/+bug/1303369

So, no other way except changing the Device memory into Non-cached memory and use sync instructions.

Never set Device memory as Ethernet Buffer. You will be in trouble!

Places to visit

https://blog.weekendthrill.com/top-30-camping-places-around-chennai/

Windows 10 Recovery key

Linux Ethernet drivers for RZ/A1

https://github.com/renesas-rz/linux-3.14/tree/master/drivers/net/ethernet/renesas

sh_eth.c & sh_eth.h are the ethernet drivers for RZ/A1.

Hook routines

When hook routines are enabled, after one hook function call, the execution went to invalid address locations. When the it is disabled, the program works fine. When I changed to SVC mode, then also it was working fine. When analyzing, the stack used was the previous task's stack pointer.

So, when checking a function call, not only check whether the registers are properly saved and returned. But, also check the stack used is not corrupting others. Even when checking a function, check once with changing the stack pointer.

JTAG connector

http://www.kmckk.co.jp/jet2/probe-manual-img/jet2_arm20toCTX.pdf

ARM interrupt handling

https://ece.umd.edu/class/enee447.S2016/ARM-Documentation/ARM-Interrupts-1.pdf

Autosar

http://www.rroij.com/open-access/an-overview-of-autosar-multicore-operating-system-implementation-.php?aid=46277

Using Power Bank/Pack to power the boards

Powering arduino UNO+microservo off power bank

https://electronics.stackexchange.com/questions/286535/powering-arduino-unomicroservo-off-power-bank

How can I signal a USB charger to provide power?

https://electronics.stackexchange.com/questions/391444/how-can-i-signal-a-usb-charger-to-provide-power

Powering Arduino from a power bank (Read 23762 times)

https://forum.arduino.cc/index.php?topic=305175.0

TalentCell Rechargeable 12V 6000mAh/5V 12000mAh

https://www.amazon.com/gp/product/B00ME3ZH7C/ref=oh_aui_detailpage_o09_s00?ie=UTF8&psc=1

TalentCell Rechargeable 12V 6000mAh/5V 12000mAh DC Output Lithium Ion Battery Pack For LED Strip And CCTV Camera Portable Li-ion Battery Bank With Charger Black (Multi-led indicator)

https://www.amazon.in/TalentCell-Rechargeable-12000mAh-Multi-led-indicator/dp/B00ME3ZH7C

MCIMX6DL-SDP

https://www.components-center.com/jp/product/NXP-USA-Inc/MCIMX6DL-SDP.html

Porting MII to RMII

When RMII is added check the following:

1) CPU should have the selector bit to choose between MII and RMII. Make sure the RMII mode is selected.

2) In RMII, the MAC should be configured for Speed (10/100) and Duplex manually. Please check whether the code configures it correctly. MII may require only the Duplex to be set manually.

3) In same way as of 1), if the PHY supports both MII/RMII, the PHY should be configured for RMII. And, also check for additional settings for RMII.

4) In RMII, the 50MHz Reference clock needs to be supplied. Please check that clock supply has been enabled.

5) Finally, the GPIO settings that is subset of MII.

Rene

r_cpg_lld_rza2m.c

/*! EXTAL frequency (khz) */
static double_t gs_cpg_extal_frequency_khz = 24000.0;
/*! PLL frequency (khz) */
static double_t gs_cpg_pll_frequency_khz = 1056000.0;
/*! ICLK divisor */
static uint32_t gs_cpg_iclk_divisor = 2;
/*! ICLK frequency (khz) */
static double_t gs_cpg_iclk_frequency_khz = 528000.0;
/*! BCLK divisor */
static uint32_t gs_cpg_bclk_divisor = 8;
/*! BCLK frequency (khz) */
static double_t gs_cpg_bclk_frequency_khz = 132000.0;
/*! P1CLK divisor */
static uint32_t gs_cpg_p1clk_divisor = 16;
/*! P1CLK frequency (khz) */
static double_t gs_cpg_p1clk_frequency_khz = 66000.0;

Sleep mode in RZ/A1L

https://www.renesas.com/us/en/doc/products/mpumcu/tu/002/tnrza003ae.pdf

OMAPL137 to OMAPL138 migration

System Timer Interrupt
DDR Address
Interrupt Numbers

OMAP-L137 to OMAP-L138 Migration
http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/99134

ARM articles

Barrier instruction and Write buffer/Store buffer

https://www.aps-web.jp/academy/ca/11/

Cortex-R4: Difference between Normal and Device memory

Cortex™-R4 and Cortex-R4F Technical Reference Manual

Check the corresponding architecture's manual for "Write buffer", "Device memory" to know about the attributes more precisely.

--
Memory that is marked as Strongly-ordered or Device type is typically sensitive to the number
of reads or writes performed. Because of this, instructions that access Strongly-ordered or
Device memory are never abandoned when they have started accessing memory. These
instructions always complete either all or none of their memory accesses.
--
The processor memory system contains a store buffer that helps to improve the throughput of
accesses to Normal type memory. See Store buffer on page 8-18 for more information. Because
of the ordering rules that they must follow, accesses to other types of memory typically have a
lower throughput or higher latency than accesses to Normal memory. In particular:
• reads from Device memory must first drain the store buffer of all writes to Device memory
• all accesses to Strongly-ordered memory must first drain the store buffer completely.
Similarly, when it accesses Strongly-ordered or Device type memory, the processor's response
to interrupts must be modified, and the interrupt response latency is longer. See Low interrupt
latency on page 3-17 for more information.
To ensure optimum performance, you must understand the architectural semantics of the
different memory types. Use Device memory type for appropriate memory regions, typically
peripherals, and only use Strongly-ordered memory type for memory regions where it is
essential.
--
Store buffer merging
The store buffer has merging capabilities. If a previous write access has updated an entry, other
write accesses on the same line can merge into this entry. Merging is only possible for stores to
Normal memory.
Merging is possible between several entries that can be linked together if the data inside the
different entries belong to the same cache line.
No merging occurs for writes to Strongly-ordered or Device memory. The processor
automatically drains the store buffer as necessary, before performing Strongly-ordered accesses
or Device reads.
--
The store buffer is drained of all stores to Device memory before a load is performed from
Device memory.
--
Load and store instructions to Non-cacheable memory might not result in an AXI transfer
because the data might either be retrieved from, or merged into the internal store data buffers.
The exceptions to this are loads or stores to Strongly-ordered or Device memory. These always
result in AXI transfers.
--
A load or store instruction to or from Strongly-ordered or Device memory always generates AXI
transactions of the same size as implied by the instruction. All accesses using LDM, STM, LDRD, or
STRD instructions to Strongly-ordered or Device memory occur as 32-bit transfers.
--

Memory Region attribute

LPC54608 Could not debug

Regaining debug access to target MCU

https://community.nxp.com/thread/389112

ISP Reset over debug

https://community.nxp.com/thread/389040


ECRP setting examples
C:\Keil_v5\ARM\Pack\Keil\LPC54000_DFP\2.6.0\Device\Source\ARM\startup_LPC54608.s
C:\Keil_v5\ARM\Pack\Keil\LPC54000_DFP\2.6.0\Device\Source\IAR\startup_LPC54608.s


Debugger hang when running ttcp -t and ttcp -r simultaneously.
Increase the stack size of Rx and Tx tasks of ttcp program.

LPC54608 Ethernet Driver

https://www.oryx-embedded.com/doc/lpc54608__eth__driver_8c_source.html

Undefined reference to _write

Sprintf usage in Xilinx GNUM

GNU Arm Embedded Toolchainとシステムコールの実装について

https://qiita.com/takahashim/items/120d69a44a80d08b70e7


Libnosys implementation
https://github.com/eblot/newlib/tree/master/libgloss/libnosys

Convert PDF to JPG

http://pdftoimage.com/

NIOS Release notes

https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/rn/rn-eds003-1_0.pdf

PPP mdm_init takes a lot of time and thus ping does not respond for long

The disconnection may be improper (for example, without proper close, the debugger is restarted) due to which the modem is in improper state and the mdm_init does not get fast initialization sequence. When the modem is powered off and on or once the connection is established after long time and properly closed, it will connect very fast from next time.

Problems compilation

CEV-RZA1L
In IPv6 Thumb mode program, the ftp takes so much time (around 17seconds) after displaying Opening data connection. There was no issues withing a second, it happened in ARM mode.

Do not know. It automatically disappeared while investigating. May be some memory window was opening. That effect??

ARM compiler: VFP compilation

>armasm --cpu list

 --cpu=Cortex-A15
 --cpu=Cortex-A15.no_neon
 --cpu=Cortex-A15.no_neon.no_vfp

>armasm --fpu list

 --fpu=VFPv3
 --fpu=VFPv3_FP16
 --fpu=VFPv3_D16
 --fpu=VFPv3_D16_FP16
 --fpu=VFPv2
 --fpu=VFPv4
 --fpu=VFPv4_D16
 --fpu=FPv4-SP
 --fpu=FPv5_D16
 --fpu=FPv5-SP
 --fpu=SoftVFP
 --fpu=SoftVFP+VFPv2
 --fpu=SoftVFP+VFPv3
 --fpu=SoftVFP+VFPv3_FP16
 --fpu=SoftVFP+VFPv3_D16
 --fpu=SoftVFP+VFPv3_D16_FP16
 --fpu=SoftVFP+VFPv4
 --fpu=SoftVFP+VFPv4_D16
 --fpu=SoftVFP+FPv4-SP
 --fpu=SoftVFP+FPv5_D16
 --fpu=SoftVFP+FPv5-SP
 --fpu=None


In ARM compiler, there is no independent flags to specify the D16/D32 and VFPv3/VFPv4 to make the combinations. Instead, the combinations are clubbed together internally. So, there is no other way than just considering __TARGET_FPU_VFPV4/__TARGET_FPU_VFPV3 as "VFP with D32", unlike IAR EWARM. And, NEON does not come into picture in deciding the context in Kernel or SIMD is used in Kernel library.

Tax calculator

https://www.livemint.com/Object/0pTggtxaMK1S6N9j6jHPZL/tax-calculator-2018.html

Debugging EWARM program using CCS

How to use CCS to debug programs created by IAR EW
https://www.youtube.com/watch?v=UZkq4RhH0pg

Semihosting a problem

Any issue like "does not return from Sysini()", "though system is working but very slow", Semihosting is a problem.

Or, Vector Table (SVC vector) is placed in wrong(unexpected) location.

Business tourism

https://www.active-consulting.es/en/tourism/business-tourism

STM32F756G-EVAL 10 Mbps Half duplex not working

  /* Configure PA0
  GPIO_InitStructure.Pin =  GPIO_PIN_0;
  HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);

  Note: Ethernet Full duplex mode works properly in the default setting
  (which MII_CRS is not connected to PA0 of STM32F756NGH6) because PA0 is shared
  with MC_ENA.
  If Half duplex mode is needed, uncomment PA0 configuration code source (above
  the note) and close the SB36 solder bridge of the STM32756G-EVAL board .
  */

  /* Configure PH3
  GPIO_InitStructure.Pin =  GPIO_PIN_3;
  HAL_GPIO_Init(GPIOH, &GPIO_InitStructure);

  Note: Ethernet Full duplex mode works properly in the default setting
  (which MII_COL is not connected to PH3 of STM32F756NGH6) because PH3 is shared
  with SDRAM chip select SDNE0.
  If Half duplex mode is needed, uncomment PH3 configuration code source (above
  the note) and close SB47 solder bridge of the STM32756G-EVAL board.
  */

  /* Configure PI10
  GPIO_InitStructure.Pin = GPIO_PIN_10;
  HAL_GPIO_Init(GPIOI, &GPIO_InitStructure);

  Note: Ethernet works properly in the default setting (which RX_ER is not
  connected to PI10 of STM32F756NGH6) because PI10 is shared with data signal
  of SDRAM.
  If RX_ER signal is needed, uncomment PI10 configuration code source (above
  the note) then remove R248 and solder SB9 of the STM32756G-EVAL board.
  */

Look at the source:

C:\Keil_v5\ARM\Pack\Keil\STM32F7xx_DFP\2.9.0\Projects\STM32756G_EVAL\Applications\LwIP\LwIP_HTTP_Server_Raw\Src\ethernetif.c

https://www.keil.com/boards2/stmicroelectronics/stm32756g_eval/#/eula-container

Modem

http://www.hayesmicro.com/products/index.html

Car comparison

https://www.quora.com/Which-is-the-most-comfortable-five-seater-hatchback-in-India

Factors to be available:
・Reclined rear seats for comfort, sleep and long travel
・More boot space
・larger windows and brighter (White, not black) cabin color
・High road clearance

Honda Jazz
・Check for reclined rear seats and Magic seat
・Seems to have flat floor surface
--
Further, the Jazz is the only hatchback in the market to get reclining rear seats, and also has a flat floor at the back (no hump due to the transmission tunnel). The rear seats also have the 'magic seats' trick, giving them a lot of flexibility.

I have taken test drive of Jazz, Baleno, Ford Figo, VW Polo, etc. I liked the Jazz the best. Only problem was I wanted automatic and top end Jazz (with magic seats) was not available with auto transmission. I went for Ford EcoSport instead. Baleno is quite good and VFM too but the rear seats are not comfy and have hard suspension, thus bumpy ride.
--

New Honda Jazz vs Hyundai i20: Specifications comparison

https://www.autocarindia.com/car-news/new-honda-jazz-vs-hyundai-i20-specifications-comparison-395862

Ground clearance: Jazz (165mm)  i20 (170mm) BR-v (210mm) Wagon-R (165 mm) kwid (180 mm)

When it comes to ground clearance, the Vitara Brezza comes second with 198 mm, just a shade under the Duster’s 205 mm.

The S-Cross has the lowest ground clearance at 180 mm while the Creta is in-between at 190 mm.

Swift (163 mm) 

• Suzui Dezire 170 mm

RZ/G1E DDR initialization

http://www.lineo.co.jp/rzg-pf/data/iW-RainboW-G22D-SODIMM_Evaluationkit_operation_wqmanual_v1.0.pdf

https://github.com/renesas-rz/meta-renesas/blob/master/meta-rzg1/recipes-kernel/linux/linux-renesas/skrzg1e/0002-Add-pwm-support-on-device-tree-for-skrzg1e-board.patch


iWave Board Patch referred for EthernetAVB (search for CONFIG_SH_ETHER_RAVB)
SOURCE~1\Linux\Yocto\PATCH003-iW-PREZZ-SC-01-R2.0-REL1.0-YoctoDaisy_basic_customization.patch

https://github.com/renesas-rz/meta-renesas/blob/master/meta-rzg1/recipes-bsp/u-boot/u-boot/PATCH001-iW-PREZZ-SC-01-R2.0-REL1.0-Linux3.10.31-UBoot_basic_customization.patch

Booting user program via U-Boot

AM335x U-Boot User's Guide

http://processors.wiki.ti.com/index.php/AM335x_U-Boot_User's_Guide

TI ARM compiler manuals

ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide
http://www.ti.com/lit/ug/spnu151r/spnu151r.pdf

RZ/T1 Ethernet Driver

RZ/T1 Group Multi Port Ethernet Driver
https://www.renesas.com/en-us/doc/products/mpumcu/apn/rz/r01an3501ej0110-rzt1.pdf

CSIDE PALMiCE files
https://www.computex.co.jp/products/palmice3/arm.htm

Cortex-M3/M4 Debugging

Good post to change Imprecise abort to Precise by disabling buffering ((DISDEFWBUF bit in ACTLR register)
http://chmorgan.blogspot.in/2013/06/debugging-imprecise-bus-access-fault-on.html

In your OS, specially in Cortex-M3/M4 a good step would be disabling of nested interrupts by setting same interrupt priority level for all interrupts.

Bus fault (imprecise error) occurs in peak busy state, if number of bits for PRIORITY GROUP and PRIORITY LEVEL are not properly set in n4ixxxx.c.

CCS Project settings

New-> CCS Project -> Target = K2GEVM


VFP -> vfplib
Remove NEON
C:\X\INC
n4e7aal.lib
C:\X\LIB\ARM\CCS7
10063
10068
__RESET
"STACK=0x800FC000"
Unaligned access = off
enum_type = int

For debugger,

select new -> Target configuration -> Select Board Target Name. (Not CPu name, then only all the board configuration will be available). For example, AM437x Starter Kit, it will be SK_AM4374.
Then, use the device configuration in Debug window.

NIOS Quartus Prime GCC version

Quartus Prime Lite and Standard version seems to be stopped in 19.1. Only Quartus Pro seems to be released 19.2, 19.1 etc. For you, only the GCC version matters. So, just build and keep the libraries for different version of GCC available till the latest version. Also, the pro edition seems to be supporting only Family 10 FPGAs like Arria 10, Cyclone 10 and Stratix 10.

GCC 12.2.1 (Quartus Prime v23.2 Pro) - Last version. In v24.1, there is no Nios II

GCC 11.3.1 (Quartus Prime v22.3 Pro)

GCC 11.2.1 (Quartus Prime v22.1 Pro, v22.2 Pro)

GCC 10.3.1 (Quartus Prime v21.4 Pro) 

GCC 10.3.1 (Quartus Prime v21.3 Pro/ v21.1 lite/ v21.1 standard)

GCC 10.2.1 (Quartus Prime v21.2 Pro)

GCC 10.2.1 (Quartus Prime v21.1 Pro) - Kosu PC

GCC 10.2.1 (Quartus Prime v20.4 Pro)  - Prashant PC
GCC 10.1.1 (Quartus Prime v20.3 Pro)  - Prashant PC
GCC 10.1.1 (Quartus Prime v20.1.1 lite)  - Tarur

GCC 9.3.1 (Quartus Prime v20.2 Pro)  - Prashant PC
GCC 9.2.1 (Quartus Prime v20.1 Pro)  -    " (able to install multiple versions)
GCC 8.3.1 (Quartus Prime v19.4 Pro)  - Installed in Prashant PC.
GCC 8.3.1 (Quartus Prime v19.3 Pro)  - Use 19.4 pro
GCC 8.3.1 (Quartus Prime v19.2 Pro)  - Use 19.4 pro
GCC 8.3.1 (Quartus Prime v19.1 lite)  - Use 19.4 pro
GCC 7.3.1 (Quartus Prime v19.1 Pro) - Subash computer
GCC 7.3.1 (Quartus Prime v18.1 Pro) - Use 19.1 pro
                       ↑ Pro
GCC 5.3.0 (Quartus Prime v18.1 Lite and Std) - Do not know how to download Std. Lite in my Computer
GCC 5.3.0 (Quartus Prime v17.1)  - (No. 18.1 is used instead)
 GCC 5.2.0 (Quartus Prime v16.0)  - Nav computer
 GCC 4.9.2 (Quartus Prime v15.1)  - Eli computer
 GCC 4.8.3 (Quartus II v14.1)     - Takur computer
 GCC 4.7.3 (Quartus II v13.1)     - Eli computer
 GCC 4.1.2 (Quartus II v10.0 ～ v13.0 SP1) - Eli computer

Reference design

Serial is tested with dev.

Max 10 reference design is taken from server. UART is not checked. May be there is no reference design that supports UART. -DUART is not used.

18.1 and other release notes:
https://www.intel.cn/content/www/cn/zh/programmable/documentation/lro1465407474833.html
https://www.intel.com/content/www/us/en/programmable/documentation/lro1465407474833.html

Installation from Quartus Prime 19.2 Pro....
https://kiazhi.github.io/blog/The-easy-way-to-get-Ubuntu-18.04-distro-environment-on-Windows/
https://superuser.com/questions/1359633/apt-get-install-is-not-working-in-wsl
https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2019/why-does-the-nios--ii-not-installed-after-full-installation-of-t.html

For Arria 10,

 jtagconfig.exe --setparam 1 JtagClock 16M

/devices/10AS066H1(.|ES)|10AS066H2|..@1#USB-1
/devices/5M(1270ZF324|2210Z)|EPM2210@3#USB-1
/devices/5M(1270ZF324|2210Z)|EPM2210@4#USB-1

As mentioned in the PDF of Example Application Ethernet project folder,

nios2-download  -g a10_fpga_sgmii_enet1.elf && nios2-terminal.exe

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/embedded/2019/error--failed-to-execute--wsl---create-this-bsp-no-make.html

MicroBlaze MBAR instruction restriction

No delay slot restriction in EDK 14.1 (MicroBlaze v8.30)
https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/mb_ref_guide.pdf#page=205


Delay slot restriction entered in EDK 14.2 (MicroBlaze v8.40)
https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/mb_ref_guide.pdf#page=207