Wednesday, September 5, 2018

Rene

r_cpg_lld_rza2m.c

/*! EXTAL frequency (khz) */
static double_t gs_cpg_extal_frequency_khz = 24000.0;
/*! PLL frequency (khz) */
static double_t gs_cpg_pll_frequency_khz = 1056000.0;
/*! ICLK divisor */
static uint32_t gs_cpg_iclk_divisor = 2;
/*! ICLK frequency (khz) */
static double_t gs_cpg_iclk_frequency_khz = 528000.0;
/*! BCLK divisor */
static uint32_t gs_cpg_bclk_divisor = 8;
/*! BCLK frequency (khz) */
static double_t gs_cpg_bclk_frequency_khz = 132000.0;
/*! P1CLK divisor */
static uint32_t gs_cpg_p1clk_divisor = 16;
/*! P1CLK frequency (khz) */
static double_t gs_cpg_p1clk_frequency_khz = 66000.0;

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