PHY access in NIOS

There is common bus for all PHY devices. But, there is facility to map maximum of two devices at the same time.

The following is wrong.
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So, when the MDIO Address 0 Register is written with any PHY Address, corresponding PHY registers are mapped to MDIO Space 0. Similarly, when MDIO Address 1 Register is written with a PHY address, that PHY will be mapped to MDIO Space 1.

So, there should be fixed PHY address for each channel. PHY Address 0 should be written to MDIO address 0 and MDIO Space 0 should be accessed in phynios.c. Similarly, all 1 should be accessed in second channel driver.
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Each MAC (TSE0 & TSE1) can map up to two PHY devices in either  MDIO Space 0 or MDIO Space1. The offset for MDIO Space 0 = 0x200 (Base offset in manual * 4). But, why do I need two PHYs for single mac? So, I just use MDIO Space 0 for mapping the corresponding PHY in each channel.

See below. Without any doubt, the instances share MDIO master. So, single shared MDIO bus.