Pugin development for Eclipse

https://www.amazon.com/gp/product/0672326108?ie=UTF8&tag=ladybuguniver-20&linkCode=as2&camp=1789&creative=9325&creativeASIN=0672326108

Writing an Eclipse Plug-in (Part 1)- What I’m going to do

https://cvalcarcel.wordpress.com/2009/07/08/writing-an-eclipse-plug-in-part-1-what-im-going-to-do/

How to write a plugin for Eclipse? [closed]

https://stackoverflow.com/questions/299283/how-to-write-a-plugin-for-eclipse

PIC32MZ CPU

https://en.wikipedia.org/wiki/PIC_microcontrollers#PIC32MZ
PIC32MZ series of microcontrollers, based on the MIPS M14K core. 

MIPS M14K core
https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00666-2B-M14K-DTS-02.05.pdf

https://www.mips.com/products/aptiv/microaptiv/

microAptiv MCU? microAptiv MPU?

RZ/N1D

RZ/N1 Solution Kits
https://www.renesas.com/eu/en/doc/products/mpumcu/doc/rz/R12PF0010ED0300.pdf

CPU Board Features
 ● RZ/N1Dx device on the RZ/N1D-DB
 ● RZ/N1S device on the RZ/N1S-DB
 ● Fast Ethernet (MII/RMII) (2 x)
 ● NOR flash, DDR3 (only on RZ/N1D-DB)
 ● USB Device/Host
 ● Serial USB debug/power port
 ● User LEDs, User switches, GPIOs, …

Expansion Board Features
 ● Gbit Ethernet (RGMII/MII) (3 x)
 ● SDIO interface
 ● PMODS (4 x)
 ● Parallel Interface
 ● LCD display interface
 ● CAN, RS485, RS232

● RZ/N1D Solution Kit: YCONNECT-IT-RZN1D
● Expansion Board: YCONNECT-IT-RZN1-EB

RZ/N1D搭載 CPUボード
https://www.apnet.co.jp/images/global/et/2017/leaf_rzn-0a.pdf

RZ/N1D U-Boot

U-Boot Git

https://github.com/renesas-rz/rzn1_u-boot

All repos

https://github.com/orgs/renesas-rz/repositories?page=2

Linux

https://github.com/renesas-rz/rzn1_linux

NIOS II Gen2

│Nios II Gen2 Migration Guide
│https://www.intel.com/content/www/us/en/programmable/documentation/iga1432837083642.html
：
│Software Limitations - Uncached Memory Regions

│What do I need to do/be aware of when upgrading my software from Nios II Classic (Gen1) to Nios II Gen2 processors?
│https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd07072014_334.html

[NiosII][組込] NiosII コアを/fにしてD-cacheを有効にする場合の注意

https://www.ujiya.net/fpga/0142


https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/nios2/n2sw_nii52007_j.pdf


NIOS II e -> No data cache, No instruction cache. So, No cache bypass required.
NIOS II f -> Like normal processor, it has caches. But, MMU is optional. If MMU, 32 bit address width and Cacheability is configured via TLB. If, no MMU, 31 bit address width and 31st bit is used for cache bypass (non-caching address).

For Gen2, the alignment of non-cacheable memory should be multiple of 32 as the Cache snooping does not exist here.

Use, HAL functions!

It has optional MMU and I think iOS does not consider MMU presence in both NIOS II classic and GEN2

i.MX6 SD Boot

https://community.nxp.com/docs/DOC-339750

Look at the \\sempc1\boards folder


=> mmc dev 1
switch to partitions #0, OK
mmc1 is current device
=> mmc rescan
=> fatls mmc1
** No device specified **
=> fatls mmc 1
** Unrecognized filesystem type **
=> fatls mmc 1

https://www.nxp.com/docs/en/user-guide/i.MX_BSP_Porting_Guide_Linux.pdf

i.MX6Q-SDB board bringup with Linux
https://community.nxp.com/thread/327786

Preparing i.MX6 to boot from SD Card

http://referencedesigner.com/blog/preparing-i-mx6-to-boot-from-sd-card/6853/


http://referencedesigner.com/blog/booting-i-mx6-directly-from-sd-card/2303/

i.MX BSP Porting Guide
https://www.nxp.com/docs/en/user-guide/i.MX_BSP_Porting_Guide_Linux.pdf

Cortex-R4 MPU setting

ARM Kernel Understanding

ARM Kernel Understanding:

You know that the IRQ handler saves the following Ten registers initially in the IRQ stack.

;    + 0|__U_sp__|
;    + 4|__U_lr__|
;    + 8|___r0___|
;    +12|___r1___|
;    +16|___r2___|
;    +20|___r3___|
;    +24|__dummy_| .. scratch(r0)
;    +28|__spsr__|
;    +32|__r12___|
;    +36|_lr(pc)_|

When this is first interrupt, all this registers are transferred to above the Task's stack (User SP) and the volatile registers of the context structure is formed. And, the User stack pointer is saved at the TCB of the task. This stack pointer is later acquired from the TCB of the task in the ret_int.

Since the mode is changed to the System mode at the end of ent_int, the ISP is assigned to the User stack pointer and further interrupt handler processing and further nested interrupt context saving is performed in the ISP. (Nested interrupt context saving is performed only in the IRQ stack, not ISP. ISP is only for the Interrupt handler processing)

The question remaining here is howmany registers are still remaining in the IRQ stack after transferring the stacked registers using ldfmd and how are they used?

When this is nested interrupt, the IRQ stack is not disturbed, but the VFP volatile registers too saved in the IRQ stack in case of VFP is enabled in the interrupt handler using ena_vpu() call. The ISP is used only for the Interrupt Handler processing.