Thursday, February 14, 2019

NIOS II Gen2

│Nios II Gen2 Migration Guide
https://www.intel.com/content/www/us/en/programmable/documentation/iga1432837083642.html

│Software Limitations - Uncached Memory Regions

│What do I need to do/be aware of when upgrading my software from Nios II Classic (Gen1) to Nios II Gen2 processors?
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd07072014_334.html

[NiosII][組込] NiosII コアを/fにしてD-cacheを有効にする場合の注意

https://www.ujiya.net/fpga/0142


https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/nios2/n2sw_nii52007_j.pdf


NIOS II e -> No data cache, No instruction cache. So, No cache bypass required.
NIOS II f -> Like normal processor, it has caches. But, MMU is optional. If MMU, 32 bit address width and Cacheability is configured via TLB. If, no MMU, 31 bit address width and 31st bit is used for cache bypass (non-caching address).

For Gen2, the alignment of non-cacheable memory should be multiple of 32 as the Cache snooping does not exist here.

Use, HAL functions!

It has optional MMU and I think iOS does not consider MMU presence in both NIOS II classic and GEN2

No comments:

Post a Comment