Tuesday, September 11, 2018
Sunday, September 9, 2018
Porting MII to RMII
When RMII is added check the following:
1) CPU should have the selector bit to choose between MII and RMII. Make sure the RMII mode is selected.
2) In RMII, the MAC should be configured for Speed (10/100) and Duplex manually. Please check whether the code configures it correctly. MII may require only the Duplex to be set manually.
3) In same way as of 1), if the PHY supports both MII/RMII, the PHY should be configured for RMII. And, also check for additional settings for RMII.
4) In RMII, the 50MHz Reference clock needs to be supplied. Please check that clock supply has been enabled.
5) Finally, the GPIO settings that is subset of MII.
1) CPU should have the selector bit to choose between MII and RMII. Make sure the RMII mode is selected.
2) In RMII, the MAC should be configured for Speed (10/100) and Duplex manually. Please check whether the code configures it correctly. MII may require only the Duplex to be set manually.
3) In same way as of 1), if the PHY supports both MII/RMII, the PHY should be configured for RMII. And, also check for additional settings for RMII.
4) In RMII, the 50MHz Reference clock needs to be supplied. Please check that clock supply has been enabled.
5) Finally, the GPIO settings that is subset of MII.
Wednesday, September 5, 2018
Rene
r_cpg_lld_rza2m.c
/*! EXTAL frequency (khz) */
static double_t gs_cpg_extal_frequency_khz = 24000.0;
/*! PLL frequency (khz) */
static double_t gs_cpg_pll_frequency_khz = 1056000.0;
/*! ICLK divisor */
static uint32_t gs_cpg_iclk_divisor = 2;
/*! ICLK frequency (khz) */
static double_t gs_cpg_iclk_frequency_khz = 528000.0;
/*! BCLK divisor */
static uint32_t gs_cpg_bclk_divisor = 8;
/*! BCLK frequency (khz) */
static double_t gs_cpg_bclk_frequency_khz = 132000.0;
/*! P1CLK divisor */
static uint32_t gs_cpg_p1clk_divisor = 16;
/*! P1CLK frequency (khz) */
static double_t gs_cpg_p1clk_frequency_khz = 66000.0;
/*! EXTAL frequency (khz) */
static double_t gs_cpg_extal_frequency_khz = 24000.0;
/*! PLL frequency (khz) */
static double_t gs_cpg_pll_frequency_khz = 1056000.0;
/*! ICLK divisor */
static uint32_t gs_cpg_iclk_divisor = 2;
/*! ICLK frequency (khz) */
static double_t gs_cpg_iclk_frequency_khz = 528000.0;
/*! BCLK divisor */
static uint32_t gs_cpg_bclk_divisor = 8;
/*! BCLK frequency (khz) */
static double_t gs_cpg_bclk_frequency_khz = 132000.0;
/*! P1CLK divisor */
static uint32_t gs_cpg_p1clk_divisor = 16;
/*! P1CLK frequency (khz) */
static double_t gs_cpg_p1clk_frequency_khz = 66000.0;
Thursday, August 30, 2018
Friday, August 24, 2018
OMAPL137 to OMAPL138 migration
System Timer Interrupt
DDR Address
Interrupt Numbers
OMAP-L137 to OMAP-L138 Migration
http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/99134
DDR Address
Interrupt Numbers
OMAP-L137 to OMAP-L138 Migration
http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/99134
Wednesday, August 22, 2018
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