Wednesday, November 8, 2017

Cygwin Mount on Windows 7

With latest cygwin setup ver 2.882, NFS is as follows,

http://www.morethantechnical.com/2014/01/08/share-nfs-from-windows/

except the following step is not needed, as it gives the ESTALE error if the file system which is going to be mounted is already a mounted one.

----
"5. Due to a strange behavior of Cygwin, you must remount your desired drive as a different mount 
mkdir -p /mnt/d

mount d:/ /mnt/d/
----
Instead I just created a directory as follows,

mkdir -p /mnt/testu

and assigned the owner which automatically had the user and group of "tarner (windows user name)" and "None" respectively. It has "drwxr_xr_x+".
And, added it to /etc/exports as
/mnt/testu (rw,all_squash,anonuid=1000,anongid=513)

And, the following also was not there. It displayed some error. But, it does not matter.


        cygrunsrv --start portmap
    The Linux command was,

    mount -v -t nfs -o vers=2 192.168.0.35:/mnt/testu share

    If Linux, please try any command with -v option to debug easily which is verbose.

    Tuesday, October 31, 2017

    Why do we need a capacitor?

    https://www.khanacademy.org/questions/why-do-we-need-a/kafb_5416137

    Capacitor is used as Dam which will convert the disasters to boon by buffering the wild and irregular flow of water in streams. When surplus flow, it will absorb and when needed it can supply as much as its capacity.


    Friday, October 13, 2017

    Running both cores in Xilinx SDK





    First run cpu0 and then cpu1. otherwise, the interrupt settings by CPU1 will be erased and initiailized by CPU0. So, the LEDs won't glow.

    Thursday, September 21, 2017

    Thursday, August 17, 2017

    NEON:VFP Registers 64 bit

    • VFPv1 - obsoleted by ARM
    • VFPv2 - optional on ARMv5 and ARMv6 cores
      • Supports standard FPU arithmetic (add, sub, neg, mul, div), full square root
      • 16 64-bit FPU registers
    • VFPv3[-D32]
      • Broadly compatible with VFPv2 but adds
        • Exception-less FPU usage
        • 32 64-bit FPU registers as standard
        • Adds VCVT instructions to convert between scalar, float and double.
        • Adds immediate mode to VMOV such that constants can be loaded into FPU registers
    • VFPv3-D16
      • As above, but only has 16 64-bit FPU registers in VFPv3-D16 variant
    • VFPv3-F16 variant
      • Uncommon but supports IEEE754-2008 half-precision (16-bit) floating point
    • VFPv4
      • Cortex-A5
      • Has a "fused multiply-accumulate"