NEON:VFP Registers 64 bit

https://wiki.debian.org/ArmHardFloatPort/VfpComparison

• VFPv1 - obsoleted by ARM
• VFPv2 - optional on ARMv5 and ARMv6 cores
  • Supports standard FPU arithmetic (add, sub, neg, mul, div), full square root
  • 16 64-bit FPU registers
• VFPv3[-D32]
  • Broadly compatible with VFPv2 but adds
    • Exception-less FPU usage
    • 32 64-bit FPU registers as standard
    • Adds VCVT instructions to convert between scalar, float and double.
    • Adds immediate mode to VMOV such that constants can be loaded into FPU registers
• VFPv3-D16
  • As above, but only has 16 64-bit FPU registers in VFPv3-D16 variant
• VFPv3-F16 variant
  • Uncommon but supports IEEE754-2008 half-precision (16-bit) floating point
• VFPv4
  • Cortex-A5
  • Has a "fused multiply-accumulate"