Xilinx AXI Ethernet

http://lxr.free-electrons.com/source/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
http://lxr.free-electrons.com/source/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c#L20


Half-Duplex Mode: When this bit is 1, the transmitter operates in
half-duplex mode. When this bit is 0, the transmitter operates in
full-duplex mode. Only full-duplex is supported so this bit should
always be set to 0.

There is basically difference between Marvell 88E1111S and 88E1011S. But, lanphy.c has 88E1011S settings for 88E1111S. Refer to the following:
https://github.com/Xilinx/u-boot-xlnx/blob/master/drivers/net/phy/marvell.c

88E1111S  Vs 88E1116R
http://svn.dd-wrt.com/browser/src/linux/universal/linux-3.12/drivers/net/phy/marvell.c?rev=22733

Microblaze version tracking

#define __GNUC__ 5

#define __GNUC_MINOR__ 2

#define __GNUC_PATCHLEVEL__ 0

For example,

http://lxr.free-electrons.com/source/include/linux/compiler.h?v=2.4.37

http://www.boost.org/doc/libs/1_61_0/boost/optional/detail/optional_config.hpp

GCC assembler comments style differs based on architecture. For PowerPC and MicroBlaze, it is #. For ARM, it is @.


SDK version GCC version
SDK 2019.1          8.2
SDK 2018.3          7.3
SDK 2018.2          7.2
SDK 2018.1          7.2
SDK 2017.4 6.2
SDK 2017.3 6.2
SDK 2016.4 5.2
SDK 2016.3 5.2
SDK 2016.1 5.2 (Upgraded to)
SDK 2015.4 4.9.2
SDK 2015.3 4.9.2
SDK 2015.1 4.9.2 (Upgraded to)
SDK 2014.1 4.8.3 (Upgraded to)
SDK 14.5/2013.1
EDK14.1 4.6.2


https://www.xilinx.com/support/answers/55776.html


GCC version comparison

https://sourceforge.net/p/stxxl/git/ci/61b7fe42d2ff7ae5157049b720793c380450c6c2/tree/include/stxxl/bits/compat/shared_ptr.h?barediff=e95b9e0556953f21f002d9128de5becbba68b98e

https://gcc.gnu.org/onlinedocs/gcc-4.0.2/cpp/Common-Predefined-Macros.html


Fast Simplex Link (FSL) Interface Description
The Fast Simplex Link bus provides a point-to-point communication channel between an output FIFO and an input FIFO.

Interrupt Level Control By Software


http://google.co.kr/patents/US20050193260

ARM floating license

Start lmtool in Vaio of your user name/download

Assign the IP/8224 in the license manager of DS-5.

LS102A Timer

https://github.com/linaro-swg/u-boot/blob/master/arch/arm/cpu/armv7/ls102xa/timer.c

http://u-boot.10912.n7.nabble.com/PATCH-v6-0-17-arm-ls102xa-Add-Freescale-LS102xA-SoC-and-LS1021AQDS-TWR-board-support-td188615.html

Color code
http://code.metager.de/source/xref/denx/u-boot/arch/arm/cpu/armv7/ls102xa/timer.c


http://www.mit.edu/afs.new/sipb/contrib/linux/drivers/clocksource/arm_arch_timer.c

arm_arch_timer.h
https://kernel.googlesource.com/pub/scm/linux/kernel/git/kishon/linux-phy/+/phy-for-4.9-resolved_v1/include/clocksource/arm_arch_timer.h


Search "sched_clock: ARM arch timer"

Good Linux Cross reference site
http://osxr.org:8080/linux/source/arch/arm/include/asm/arch_timer.h

Linux overall flow
http://www.makelinux.net/books/lkd2/ch10lev1sec5


LS1021A. SGMII
http://lxr.free-electrons.com/source/drivers/net/ethernet/freescale/gianfar.c
http://lxr.free-electrons.com/source/drivers/net/ethernet/freescale/fsl_pq_mdio.c

LPUART
https://searchcode.com/codesearch/view/57817926/

NXP Helpful queries

LS1021A. How to start secondary core in a baremetal program loaded via U-Boot?
https://community.nxp.com/thread/398648

LS1021a CSF format: entry point
https://community.nxp.com/thread/391397

Issue in Booting After Enabling Secure Boot
https://community.nxp.com/thread/385980

Detailed boot process LS1021a SD-card-boot and NOR-boot
https://community.nxp.com/thread/430105

LS1021a full boot sequence
https://community.nxp.com/thread/390833

----
Frame memory mapped for System counter is only following:

D5.3 Counter module control and status register summary

The timer frame for timers of following is not implemented:

D5.5 The CNTBaseN and CNTPL0BaseN frames

ARM® Architecture Reference Manual
ARMv7-A and ARMv7-R edition

Look at RZ/G1E sample. Generic Timer control is memory mapped. It means the Generic Timer which is just Increment Counter is enabled through Memory mapped CNTCR register. But, the Physical Timer which is a decremented counter and uses the Generic Timer pulses remains to be enabled and setting up through the assembly code. So, just the enabling code of Generic timer is added in the timer startup function.

----

Regarding booting of LS1021A, I am not sure how the RCW is formed. But, RCW image is written at the starting of NOR flash (This is not necessarily 0x00000000 address). At address 0x00000000, the PBL (Pre-Boot Loader) is running and this PBL will load the Jump address (from the RCW) to the Scratch Read / Write Register 1 (DCFG_CCSR_SCRATCHRW1) that is Entry address of program in NOR flash. The program in NOR flash needs to initialize the DDR memory.

----

RCW at starting address of NOR flash (0x60000000):

60000000: 55aa55aa 0001ee01 0a000806 00000000    .U.U............
60000010: 00000000 00000000 00000020 00794000    ........ ....@y.
60000020: 005a02e0 00600421 00000000 00000000    ..Z.!.`.........
60000030: 00000000 00800320 00000800 40731b88    .... .........s@
60000040: 00000000 00000000 00025709 ffffffff    .........W......
60000050: 58015709 00030000 7c004089 0073f421    .W.X.....@.|!.s.
60000060: 7c005089 0073f421 0002ee09 0000f867    .P.|!.s.....g...
                                                        ~~~~~~~~~~★ Entry address of program in NOR flash
60000070: 40006108 ad5985f6 ffffffff ffffffff    .a.@..Y.........

The entry address are written to Scratch Read / Write Register 1 by the command sequence.

NAND and NOR flash

Book; Building embedded systems

Multicore

PowerPC timebase synchronization

http://www.tentech.ca/2010/09/easy-multi-core-powerpc-timebase-synchronization-with-simics/

L2 Cache during MultiCore

No L2 Cache at all - Neither CPU0 nor CPU1 enabled/disabled L2 Cache
CPU0 enable L2 Cache - CPU1 should not access at all. Initialization should not do disable/enable L2 access. Application programs not only access L2 cache, but L1 cache too. Because, the data is still cached in L2 cache.

Meaning of ACTLR.smp

https://community.arm.com/thread/3092

How to divide the L2 cache between the cores on a ARM Cortex-A7?

http://stackoverflow.com/questions/30612687/how-to-divide-the-l2-cache-between-the-cores-on-a-arm-cortex-a7

Coresight Debug Insights

https://community.arm.com/groups/processors/blog/2015/07/13/how-to-debug-coresight-basics-part-3