LS102A Timer

https://github.com/linaro-swg/u-boot/blob/master/arch/arm/cpu/armv7/ls102xa/timer.c

http://u-boot.10912.n7.nabble.com/PATCH-v6-0-17-arm-ls102xa-Add-Freescale-LS102xA-SoC-and-LS1021AQDS-TWR-board-support-td188615.html

Color code
http://code.metager.de/source/xref/denx/u-boot/arch/arm/cpu/armv7/ls102xa/timer.c


http://www.mit.edu/afs.new/sipb/contrib/linux/drivers/clocksource/arm_arch_timer.c

arm_arch_timer.h
https://kernel.googlesource.com/pub/scm/linux/kernel/git/kishon/linux-phy/+/phy-for-4.9-resolved_v1/include/clocksource/arm_arch_timer.h


Search "sched_clock: ARM arch timer"

Good Linux Cross reference site
http://osxr.org:8080/linux/source/arch/arm/include/asm/arch_timer.h

Linux overall flow
http://www.makelinux.net/books/lkd2/ch10lev1sec5


LS1021A. SGMII
http://lxr.free-electrons.com/source/drivers/net/ethernet/freescale/gianfar.c
http://lxr.free-electrons.com/source/drivers/net/ethernet/freescale/fsl_pq_mdio.c

LPUART
https://searchcode.com/codesearch/view/57817926/

NXP Helpful queries

LS1021A. How to start secondary core in a baremetal program loaded via U-Boot?
https://community.nxp.com/thread/398648

LS1021a CSF format: entry point
https://community.nxp.com/thread/391397

Issue in Booting After Enabling Secure Boot
https://community.nxp.com/thread/385980

Detailed boot process LS1021a SD-card-boot and NOR-boot
https://community.nxp.com/thread/430105

LS1021a full boot sequence
https://community.nxp.com/thread/390833

----
Frame memory mapped for System counter is only following:

D5.3 Counter module control and status register summary

The timer frame for timers of following is not implemented:

D5.5 The CNTBaseN and CNTPL0BaseN frames

ARM® Architecture Reference Manual
ARMv7-A and ARMv7-R edition

Look at RZ/G1E sample. Generic Timer control is memory mapped. It means the Generic Timer which is just Increment Counter is enabled through Memory mapped CNTCR register. But, the Physical Timer which is a decremented counter and uses the Generic Timer pulses remains to be enabled and setting up through the assembly code. So, just the enabling code of Generic timer is added in the timer startup function.

----

Regarding booting of LS1021A, I am not sure how the RCW is formed. But, RCW image is written at the starting of NOR flash (This is not necessarily 0x00000000 address). At address 0x00000000, the PBL (Pre-Boot Loader) is running and this PBL will load the Jump address (from the RCW) to the Scratch Read / Write Register 1 (DCFG_CCSR_SCRATCHRW1) that is Entry address of program in NOR flash. The program in NOR flash needs to initialize the DDR memory.

----

RCW at starting address of NOR flash (0x60000000):

60000000: 55aa55aa 0001ee01 0a000806 00000000    .U.U............
60000010: 00000000 00000000 00000020 00794000    ........ ....@y.
60000020: 005a02e0 00600421 00000000 00000000    ..Z.!.`.........
60000030: 00000000 00800320 00000800 40731b88    .... .........s@
60000040: 00000000 00000000 00025709 ffffffff    .........W......
60000050: 58015709 00030000 7c004089 0073f421    .W.X.....@.|!.s.
60000060: 7c005089 0073f421 0002ee09 0000f867    .P.|!.s.....g...
                                                        ~~~~~~~~~~★ Entry address of program in NOR flash
60000070: 40006108 ad5985f6 ffffffff ffffffff    .a.@..Y.........

The entry address are written to Scratch Read / Write Register 1 by the command sequence.