https://community.arm.com/groups/processors/blog/2015/07/13/how-to-debug-coresight-basics-part-3
Thursday, September 1, 2016
Wednesday, August 31, 2016
Boot loaders
http://www.linaro.org/blog/core-dump/u-boot-on-arm32-aarch64-and-beyond/
https://github.com/linaro-swg/u-boot/tree/master/board/freescale/ls1043ardb
https://github.com/linaro-swg/u-boot
Controlling Booting in AARCH32 or AArch64.
4.3.76 Reset Management Register
Environment setup and U-Boot compile
http://developer.toradex.com/knowledge-base/build-u-boot-and-linux-kernel-from-source-code
http://www.linaro.org/blog/core-dump/u-boot-on-arm32-aarch64-and-beyond/
https://github.com/linaro-swg/u-boot/tree/master/board/freescale/ls1043ardb
https://github.com/linaro-swg/u-boot
Controlling Booting in AARCH32 or AArch64.
4.3.76 Reset Management Register
Environment setup and U-Boot compile
http://developer.toradex.com/knowledge-base/build-u-boot-and-linux-kernel-from-source-code
Tuesday, August 30, 2016
Monday, August 29, 2016
http://zedboard.org/sites/default/files/blogger_importer/08/zedboard-bring-up.html
https://github.com/zynqgeek/zed_helloworld
http://zedboard.org/content/zedboard-sdk-helloworld-example
For EDK 2016.2
https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-programming-guide/start
Xilinx Wiki
http://www.wiki.xilinx.com/MPSoC+Power+Management
AMP bare metal Vivado
http://www.wiki.xilinx.com/XAPP1079+Latest+Information
GIC - Sup's Wiki
http://ssup2.iptime.org/wiki/ARM_Generic_Interrupt_Controller_(GIC)
MIO - multiplexed I/O (MIO)
EMIO - extended multiplexed I/O interface (EMIO)
EPP - Extensible Processing Platform (EPP)
divide by zero
http://blog.kmckk.com/archives/4170081.html
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0133c/index.html
Artix-7 as PL of Zynq-7020
http://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html
Good linker script
http://hertaville.com/a-sample-linker-script.html
Cortex-A9 Active, but no Pending interrupt
https://community.arm.com/thread/8117
https://community.nxp.com/thread/314843
Source code of GIC interrupts
https://reviews.freebsd.org/file/data/mhsub6nzfe6qhdiwypgb/PHID-FILE-3inesgv5msw2u6deaswa/file
Xilinx API
https://forums.xilinx.com/xlnx/attachments/xlnx/zaps/471/1/api2.pdf
LXR - Marvell 88
http://lxr.free-electrons.com/source/drivers/net/phy/marvell.c#L614
https://lxr.missinglinkelectronics.com/uboot/drivers/net/phy/marvell.c#L283
Zynq FSBL
Software Developers Guide
https://www.xilinx.com/support/documentation/user_guides/ug821-zynq-7000-swdev.pdf
https://github.com/zynqgeek/zed_helloworld
http://zedboard.org/content/zedboard-sdk-helloworld-example
For EDK 2016.2
https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-programming-guide/start
Xilinx Wiki
http://www.wiki.xilinx.com/MPSoC+Power+Management
AMP bare metal Vivado
http://www.wiki.xilinx.com/XAPP1079+Latest+Information
GIC - Sup's Wiki
http://ssup2.iptime.org/wiki/ARM_Generic_Interrupt_Controller_(GIC)
MIO - multiplexed I/O (MIO)
EMIO - extended multiplexed I/O interface (EMIO)
EPP - Extensible Processing Platform (EPP)
divide by zero
http://blog.kmckk.com/archives/4170081.html
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0133c/index.html
Artix-7 as PL of Zynq-7020
http://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html
Good linker script
http://hertaville.com/a-sample-linker-script.html
Cortex-A9 Active, but no Pending interrupt
https://community.arm.com/thread/8117
https://community.nxp.com/thread/314843
Source code of GIC interrupts
https://reviews.freebsd.org/file/data/mhsub6nzfe6qhdiwypgb/PHID-FILE-3inesgv5msw2u6deaswa/file
Xilinx API
https://forums.xilinx.com/xlnx/attachments/xlnx/zaps/471/1/api2.pdf
LXR - Marvell 88
http://lxr.free-electrons.com/source/drivers/net/phy/marvell.c#L614
https://lxr.missinglinkelectronics.com/uboot/drivers/net/phy/marvell.c#L283
Zynq FSBL
Software Developers Guide
https://www.xilinx.com/support/documentation/user_guides/ug821-zynq-7000-swdev.pdf
Sunday, August 28, 2016
ARMv8 development
https://quequero.org/2014/04/introduction-to-arm-architecture/
ARMv8 difference
zero register - Not r0, but, r31 (WZR - 32 bit, XZR - 64 bit)
stack pointer - Not r13, but r31 (WSP - 32 bit, SP - 64 bit, 16-bytes aligned)
Link register - Not r14, but r30
Not banked, but PC is stored in Target Exception level's ELR register
CPSR - No access as register. But, instructions to atomically modify state bit fields
No direct PC access - Only ADR, ADRP, literal load and direct branches, BL and BLR
Branches, exception generation/return.
No Co-processor. System Instructions
System Register access
Cache/TLB management
VA⇔ＰＡ Translation
Barriers and CLREX
Architectural hints (WFI, etc)
Debug
No multiple LDM, STM, PUSH and POP instructions, but load-store of a non-contiguous pair of registers (LDP, STP).
Extra instructions LDNP, STNP (for atomic update of pair of pointers for example circular list inserts), PRFM (prefetch memory) instructions instruct not to cache data. ex: Streaming and Non-temporal data.
Conditional and predicated execution is not provided, such as IT instruction.
Condition to be appended with "." delimiter to the instruction.
No RRX shift and no ROR shift for ADD/SUB
FPU and NEON extended to 32 128 bit registers (V0 - V31). But, smaller registers no longer packed into larger registers. Just mapped to one-to-one to low order bits of 128-bit registers.
No Soft-Floating pointer. Hardware floating point is must for FP arithmetic.
Most integer instructions two forms to operate either on 32-bit or 64-bit. Assembly notation to distinguish between these two forms.
W - 32 bit word
X - 64 bit extended
// - comment
Same instructions, but, based on First Operand Register name the operation is different.
ADD W0, W1, W2 // add 32-bit register
ADD X0, X1, X2 // add 64-bit register
Only the following conditional:
Conditional branch: compare and branch if zero/non-zero, single bit if zero/non-zero.
Add/Subtract with carry.
Conditional select with increment, negate, invert: Conditionally select one source, or another incremented/negated/inverted/unmodified source register.
Conditional Select (move): set the destination to one of two source registers.
Conditional set: Conditionally select between 0 and 1, or -1.
Conditional compare: Sets condition flags to result of comparison or immediate value
Addressing features
Not 32 bit virtual address. But, 49 bit virtual address (MSB 8 bit of 64-bit pointer is ignored)
ARMv8 difference
zero register - Not r0, but, r31 (WZR - 32 bit, XZR - 64 bit)
stack pointer - Not r13, but r31 (WSP - 32 bit, SP - 64 bit, 16-bytes aligned)
Link register - Not r14, but r30
Not banked, but PC is stored in Target Exception level's ELR register
CPSR - No access as register. But, instructions to atomically modify state bit fields
No direct PC access - Only ADR, ADRP, literal load and direct branches, BL and BLR
Branches, exception generation/return.
No Co-processor. System Instructions
System Register access
Cache/TLB management
VA⇔ＰＡ Translation
Barriers and CLREX
Architectural hints (WFI, etc)
Debug
No multiple LDM, STM, PUSH and POP instructions, but load-store of a non-contiguous pair of registers (LDP, STP).
Extra instructions LDNP, STNP (for atomic update of pair of pointers for example circular list inserts), PRFM (prefetch memory) instructions instruct not to cache data. ex: Streaming and Non-temporal data.
Conditional and predicated execution is not provided, such as IT instruction.
Condition to be appended with "." delimiter to the instruction.
No RRX shift and no ROR shift for ADD/SUB
FPU and NEON extended to 32 128 bit registers (V0 - V31). But, smaller registers no longer packed into larger registers. Just mapped to one-to-one to low order bits of 128-bit registers.
No Soft-Floating pointer. Hardware floating point is must for FP arithmetic.
Most integer instructions two forms to operate either on 32-bit or 64-bit. Assembly notation to distinguish between these two forms.
W - 32 bit word
X - 64 bit extended
// - comment
Same instructions, but, based on First Operand Register name the operation is different.
ADD W0, W1, W2 // add 32-bit register
ADD X0, X1, X2 // add 64-bit register
ADD X0, X1, W2, SXTW // add 64-bit extended register
ADD X0, X1, #42 // add 64-bit immediate
ADD X0, X1, #42 // add 64-bit immediate
Only the following conditional:
Conditional branch: compare and branch if zero/non-zero, single bit if zero/non-zero.
Add/Subtract with carry.
Conditional select with increment, negate, invert: Conditionally select one source, or another incremented/negated/inverted/unmodified source register.
Conditional Select (move): set the destination to one of two source registers.
Conditional set: Conditionally select between 0 and 1, or -1.
Conditional compare: Sets condition flags to result of comparison or immediate value
Addressing features
Not 32 bit virtual address. But, 49 bit virtual address (MSB 8 bit of 64-bit pointer is ignored)
ARMv8 development
https://quequero.org/2014/04/introduction-to-arm-architecture/
ARMv8 difference
zero register - Not r0, but, r31
stack pointer - Not r13, but r31
Link register - Not r14, but r30
Not banked, but PC is stored in Target Exception level's ELR register
CPSR - No access as register. But, instructions to atomically modify state bit fields
No direct PC access - Only ADR, ADRP, literal load and direct branches, BL and BLR
Branches, exception generation/return.
No Co-processor. System Instructions
System Register access
Cache/TLB management
VA⇔ＰＡ Translation
Barriers and CLREX
Architectural hints (WFI, etc)
Debug
No multiple LDM, STM, PUSH and POP instructions, but load-store of a non-contiguous pair of registers (LDP, STP).
Extra instructions LDNP, STNP (for atomic update of pair of pointers for example circular list inserts), PRFM (prefetch memory) instructions instruct not to cache data. ex: Streaming and Non-temporal data.
Conditional and predicated execution is not provided, such as IT instruction.
Condition to be appended with "." delimiter to the instruction.
No RRX shift and no ROR shift for ADD/SUB
FPU and NEON extended to 32 128 bit registers. But, smaller registers no longer packed into larger registers. Just mapped to one-to-one to low order bits of 128-bit registers.
No Soft-Floating pointer. Hardware floating point is must for FP arithmetic.
Most integer instructions two forms to operate either on 32-bit or 64-bit. Assembly notation to distinguish between these two forms.
W - 32 bit word
X - 64 bit extended
// - comment
Same instructions, but, based on Register name the operation is different.
ADD W0, W1, W2 // add 32-bit register
ADD X0, X1, X2 // add 64-bit register
Only the following conditional:
Conditional branch: compare and branch if zero/non-zero, single bit if zero/non-zero.
Add/Subtract with carry.
Conditional select with increment, negate, invert: Conditionally select one source, or another incremented/negated/inverted/unmodified source register.
Conditional Select (move): set the destination to one of two source registers.
Conditional set: Conditionally select between 0 and 1, or -1.
Conditional compare: Sets condition flags to result of comparison or immediate value
Addressing features
Not 32 bit virtual address. But, 49 bit virtual address (MSB 8 bit of 64-bit pointer is ignored)
ARMv8 difference
zero register - Not r0, but, r31
stack pointer - Not r13, but r31
Link register - Not r14, but r30
Not banked, but PC is stored in Target Exception level's ELR register
CPSR - No access as register. But, instructions to atomically modify state bit fields
No direct PC access - Only ADR, ADRP, literal load and direct branches, BL and BLR
Branches, exception generation/return.
No Co-processor. System Instructions
System Register access
Cache/TLB management
VA⇔ＰＡ Translation
Barriers and CLREX
Architectural hints (WFI, etc)
Debug
No multiple LDM, STM, PUSH and POP instructions, but load-store of a non-contiguous pair of registers (LDP, STP).
Extra instructions LDNP, STNP (for atomic update of pair of pointers for example circular list inserts), PRFM (prefetch memory) instructions instruct not to cache data. ex: Streaming and Non-temporal data.
Conditional and predicated execution is not provided, such as IT instruction.
Condition to be appended with "." delimiter to the instruction.
No RRX shift and no ROR shift for ADD/SUB
FPU and NEON extended to 32 128 bit registers. But, smaller registers no longer packed into larger registers. Just mapped to one-to-one to low order bits of 128-bit registers.
No Soft-Floating pointer. Hardware floating point is must for FP arithmetic.
Most integer instructions two forms to operate either on 32-bit or 64-bit. Assembly notation to distinguish between these two forms.
W - 32 bit word
X - 64 bit extended
// - comment
Same instructions, but, based on Register name the operation is different.
ADD W0, W1, W2 // add 32-bit register
ADD X0, X1, X2 // add 64-bit register
ADD X0, X1, W2, SXTW // add 64-bit extended register
ADD X0, X1, #42 // add 64-bit immediate
ADD X0, X1, #42 // add 64-bit immediate
Only the following conditional:
Conditional branch: compare and branch if zero/non-zero, single bit if zero/non-zero.
Add/Subtract with carry.
Conditional select with increment, negate, invert: Conditionally select one source, or another incremented/negated/inverted/unmodified source register.
Conditional Select (move): set the destination to one of two source registers.
Conditional set: Conditionally select between 0 and 1, or -1.
Conditional compare: Sets condition flags to result of comparison or immediate value
Addressing features
Not 32 bit virtual address. But, 49 bit virtual address (MSB 8 bit of 64-bit pointer is ignored)
Thursday, August 11, 2016
zynq ethernet
https://github.com/littlekernel/lk/blob/master/platform/zynq/gem.c
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/net/ethernet/xilinx/xilinx_emacps.c
http://www.keil.com/dd/docs/arm/atmel/rm9200/at91rm9200.h
https://github.com/Xilinx/linux-xlnx/blob/52830813b4b1183c1dd9d664f54019be83cf335a/arch/arm/include/asm/barrier.h
Boot CPU1 in AMP mode
https://qiita.com/7of9/items/3a68aaa9ef800fa480a2
https://japan.xilinx.com/support/answers/46911.html
https://forums.xilinx.com/t5/Processor-System-Design/Bare-Metal-System-Running-on-Both-Cortex-A9-Processors/td-p/807939
https://stackoverflow.com/questions/43667647/running-xapp1079-on-a-zynq-board
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/net/ethernet/xilinx/xilinx_emacps.c
http://www.keil.com/dd/docs/arm/atmel/rm9200/at91rm9200.h
https://github.com/Xilinx/linux-xlnx/blob/52830813b4b1183c1dd9d664f54019be83cf335a/arch/arm/include/asm/barrier.h
Boot CPU1 in AMP mode
https://qiita.com/7of9/items/3a68aaa9ef800fa480a2
https://japan.xilinx.com/support/answers/46911.html
https://forums.xilinx.com/t5/Processor-System-Design/Bare-Metal-System-Running-on-Both-Cortex-A9-Processors/td-p/807939
https://stackoverflow.com/questions/43667647/running-xapp1079-on-a-zynq-board
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