https://quequero.org/2014/04/introduction-to-arm-architecture/
ARMv8 difference
zero register - Not r0, but, r31
stack pointer - Not r13, but r31
Link register - Not r14, but r30
Not banked, but PC is stored in Target Exception level's ELR register
CPSR - No access as register. But, instructions to atomically modify state bit fields
No direct PC access - Only ADR, ADRP, literal load and direct branches, BL and BLR
Branches, exception generation/return.
No Co-processor. System Instructions
System Register access
Cache/TLB management
VA⇔ＰＡ Translation
Barriers and CLREX
Architectural hints (WFI, etc)
Debug
No multiple LDM, STM, PUSH and POP instructions, but load-store of a non-contiguous pair of registers (LDP, STP).
Extra instructions LDNP, STNP (for atomic update of pair of pointers for example circular list inserts), PRFM (prefetch memory) instructions instruct not to cache data. ex: Streaming and Non-temporal data.
Conditional and predicated execution is not provided, such as IT instruction.
Condition to be appended with "." delimiter to the instruction.
No RRX shift and no ROR shift for ADD/SUB
FPU and NEON extended to 32 128 bit registers. But, smaller registers no longer packed into larger registers. Just mapped to one-to-one to low order bits of 128-bit registers.
No Soft-Floating pointer. Hardware floating point is must for FP arithmetic.
Most integer instructions two forms to operate either on 32-bit or 64-bit. Assembly notation to distinguish between these two forms.
W - 32 bit word
X - 64 bit extended
// - comment
Same instructions, but, based on Register name the operation is different.
ADD W0, W1, W2 // add 32-bit register
ADD X0, X1, X2 // add 64-bit register
Only the following conditional:
Conditional branch: compare and branch if zero/non-zero, single bit if zero/non-zero.
Add/Subtract with carry.
Conditional select with increment, negate, invert: Conditionally select one source, or another incremented/negated/inverted/unmodified source register.
Conditional Select (move): set the destination to one of two source registers.
Conditional set: Conditionally select between 0 and 1, or -1.
Conditional compare: Sets condition flags to result of comparison or immediate value
Addressing features
Not 32 bit virtual address. But, 49 bit virtual address (MSB 8 bit of 64-bit pointer is ignored)
ARMv8 difference
zero register - Not r0, but, r31
stack pointer - Not r13, but r31
Link register - Not r14, but r30
Not banked, but PC is stored in Target Exception level's ELR register
CPSR - No access as register. But, instructions to atomically modify state bit fields
No direct PC access - Only ADR, ADRP, literal load and direct branches, BL and BLR
Branches, exception generation/return.
No Co-processor. System Instructions
System Register access
Cache/TLB management
VA⇔ＰＡ Translation
Barriers and CLREX
Architectural hints (WFI, etc)
Debug
No multiple LDM, STM, PUSH and POP instructions, but load-store of a non-contiguous pair of registers (LDP, STP).
Extra instructions LDNP, STNP (for atomic update of pair of pointers for example circular list inserts), PRFM (prefetch memory) instructions instruct not to cache data. ex: Streaming and Non-temporal data.
Conditional and predicated execution is not provided, such as IT instruction.
Condition to be appended with "." delimiter to the instruction.
No RRX shift and no ROR shift for ADD/SUB
FPU and NEON extended to 32 128 bit registers. But, smaller registers no longer packed into larger registers. Just mapped to one-to-one to low order bits of 128-bit registers.
No Soft-Floating pointer. Hardware floating point is must for FP arithmetic.
Most integer instructions two forms to operate either on 32-bit or 64-bit. Assembly notation to distinguish between these two forms.
W - 32 bit word
X - 64 bit extended
// - comment
Same instructions, but, based on Register name the operation is different.
ADD W0, W1, W2 // add 32-bit register
ADD X0, X1, X2 // add 64-bit register
ADD X0, X1, W2, SXTW // add 64-bit extended register
ADD X0, X1, #42 // add 64-bit immediate
ADD X0, X1, #42 // add 64-bit immediate
Only the following conditional:
Conditional branch: compare and branch if zero/non-zero, single bit if zero/non-zero.
Add/Subtract with carry.
Conditional select with increment, negate, invert: Conditionally select one source, or another incremented/negated/inverted/unmodified source register.
Conditional Select (move): set the destination to one of two source registers.
Conditional set: Conditionally select between 0 and 1, or -1.
Conditional compare: Sets condition flags to result of comparison or immediate value
Addressing features
Not 32 bit virtual address. But, 49 bit virtual address (MSB 8 bit of 64-bit pointer is ignored)
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