Cache on Cortex-M7

MPU on Cortex-M4
https://www.st.com/resource/en/programming_manual/dm00046982-stm32-cortexm4-mcus-and-mpus-programming-manual-stmicroelectronics.pdf

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http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHEADII.html

System level cache

The Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, and Cortex-M4 processors do not have any internal cache memory. However, it is possible for a SoC design to integrate a system level cache.

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http://www.keil.com/appnotes/files/apnt_270.pdf
Migrating Application Code from ARM Cortex-M4 to Cortex-M7 Processors

https://www.keil.com/pack/doc/cmsis/Core/html/group__cache__functions__m7.html

Cache Functions (only Cortex-M7)

For Assembly routines of Cache ARM® Cortex®-M7 Devices Generic User Guide