C Runtime memory model

https://www.youtube.com/watch?v=3F3lp_F2YpQ

Workshop contents

http://www.kumikomi.net/archives/2003/05/10kumi.php
http://www.kumikomi.net/archives/2008/10/24micr4.php?page=6

EWARM Multi core debugging

https://www.youtube.com/watch?v=XNobJMoDtfE

MicroBlaze SP605 Eval board update

1) No need for CF card
- Just install EDK 14.7 in a fresh Windows 7 PC
- FPGA program the 13_2_sp605_ios_etherlite.zip

2) Debug through System Debugger is not working properly
- The Interrupt fails even with their board test programs
- So, select GDB debugger

3) When the Program goes wrong, abnormal behavior after an
interrupt,
- Check Interrupt Handler Prelog and v3_ent_int stack
adjustment
- Increase stack size
- EDK version releases need EDK/GCC versions to be
specified in Libraries

4) EDK 14.7 compiler is generating wrong code for -Os
optimization
- acre_cyc is failed with E_NOID even there are lot of
IDs

5) AXI EtherLite also works normal with 100 Mbps hub. Only Full
duplex is fixed

6) CF card too obtained with USB reader/writer and updated with
cfg0 files. But, no advantages.

TI X-loader/MOL 1st stage Bootloader to initialize SDRAM

Bootloader Project
http://omappedia.org/wiki/Bootloader_Project

3.1. U-Boot
http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components_U-Boot.html

https://stackoverflow.com/questions/34805383/why-is-mlo-needed-in-boot-step

what is the use of SPL (secondary program loader)
https://stackoverflow.com/questions/31244862/what-is-the-use-of-spl-secondary-program-loader


http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components_U-Boot.html

CCS to stop symbol at reset

JTAG Explained

https://blog.senr.io/blog/jtag-explained

Select between JTAG and SWD.
Select between Hardware / Software Reset.

IDC Male header

https://www.aliexpress.com/item/32796086136.html?spm=a2g0o.productlist.0.0.5c7a7a535R8hnU&algo_pvid=9da7e2bc-bc74-4da3-9d0d-3fb488a22a7f&algo_expid=9da7e2bc-bc74-4da3-9d0d-3fb488a22a7f-49&btsid=52c1a104-b289-4a06-ba7b-dbcad2d3ba28&ws_ab_test=searchweb0_0,searchweb201602_9,searchweb201603_55

How to add math library in CCS

GCC Cortex-A8 and Cortex-A9 predefined macros

arm-none-eabi-gcc -c -Wall -Os -mcpu=cortex-a9 -mfloat-abi=softfp -mfpu=neon -mlittle-endian -mno-unaligned-access -mno-thumb-interwork -marm -I..\..\..\INC -Wno-misleading-indentation -E -dM ..\..\..\SRC\armv7.S
#define __DBL_MIN_EXP__ (-1021)
#define __HQ_FBIT__ 15
#define __FLT32X_MAX_EXP__ 1024
#define __UINT_LEAST16_MAX__ 0xffff
#define __ARM_SIZEOF_WCHAR_T 4
#define __ATOMIC_ACQUIRE 2
#define __SFRACT_IBIT__ 0
#define __FLT_MIN__ 1.1754943508222875e-38F
#define __GCC_IEC_559_COMPLEX 2
#define __UFRACT_MAX__ 0XFFFFP-16UR
#define __UINT_LEAST8_TYPE__ unsigned char
#define __DQ_FBIT__ 63
#define __ASSEMBLER__ 1
#define __INTMAX_C(c) c ## LL
#define __ARM_FEATURE_SAT 1
#define __ULFRACT_FBIT__ 32
#define __SACCUM_EPSILON__ 0x1P-7HK
#define __CHAR_BIT__ 8
#define __USQ_IBIT__ 0
#define __UINT8_MAX__ 0xff
#define __ACCUM_FBIT__ 15
#define __WINT_MAX__ 0xffffffffU
#define __FLT32_MIN_EXP__ (-125)
#define __USFRACT_FBIT__ 8
#define __ORDER_LITTLE_ENDIAN__ 1234
#define __SIZE_MAX__ 0xffffffffU
#define __ARM_ARCH_ISA_ARM 1
#define __WCHAR_MAX__ 0xffffffffU
#define __LACCUM_IBIT__ 32
#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
#define __DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)
#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
#define __GCC_ATOMIC_CHAR_LOCK_FREE 2
#define __GCC_IEC_559 2
#define __FLT32X_DECIMAL_DIG__ 17
#define __FLT_EVAL_METHOD__ 0
#define __LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK
#define __FLT64_DECIMAL_DIG__ 17
#define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
#define __FRACT_FBIT__ 15
#define __UINT_FAST64_MAX__ 0xffffffffffffffffULL
#define __SIG_ATOMIC_TYPE__ int
#define __UACCUM_FBIT__ 16
#define __DBL_MIN_10_EXP__ (-307)
#define __FINITE_MATH_ONLY__ 0
#define __ARMEL__ 1
#define __LFRACT_IBIT__ 0
#define __GNUC_PATCHLEVEL__ 1
#define __FLT32_HAS_DENORM__ 1
#define __LFRACT_MAX__ 0X7FFFFFFFP-31LR
#define __UINT_FAST8_MAX__ 0xffffffffU
#define __has_include(STR) __has_include__(STR)
#define __DEC64_MAX_EXP__ 385
#define __INT8_C(c) c
#define __INT_LEAST8_WIDTH__ 8
#define __UINT_LEAST64_MAX__ 0xffffffffffffffffULL
#define __SA_FBIT__ 15
#define __SHRT_MAX__ 0x7fff
#define __LDBL_MAX__ 1.7976931348623157e+308L
#define __FRACT_MAX__ 0X7FFFP-15R
#define __UFRACT_FBIT__ 16
#define __ARM_FP 12
#define __UFRACT_MIN__ 0.0UR
#define __UINT_LEAST8_MAX__ 0xff
#define __GCC_ATOMIC_BOOL_LOCK_FREE 2
#define __UINTMAX_TYPE__ long long unsigned int
#define __LLFRACT_EPSILON__ 0x1P-63LLR
#define __DEC32_EPSILON__ 1E-6DF
#define __FLT_EVAL_METHOD_TS_18661_3__ 0
#define __OPTIMIZE__ 1
#define __CHAR_UNSIGNED__ 1
#define __UINT32_MAX__ 0xffffffffUL
#define __ULFRACT_MAX__ 0XFFFFFFFFP-32ULR
#define __TA_IBIT__ 64
#define __LDBL_MAX_EXP__ 1024
#define __WINT_MIN__ 0U
#define __INT_LEAST16_WIDTH__ 16
#define __ULLFRACT_MIN__ 0.0ULLR
#define __SCHAR_MAX__ 0x7f
#define __WCHAR_MIN__ 0U
#define __INT64_C(c) c ## LL
#define __DBL_DIG__ 15
#define __ARM_NEON_FP 4
#define __GCC_ATOMIC_POINTER_LOCK_FREE 2
#define __LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)
#define __SIZEOF_INT__ 4
#define __SIZEOF_POINTER__ 4
#define __USACCUM_IBIT__ 8
#define __USER_LABEL_PREFIX__
#define __STDC_HOSTED__ 1
#define __LDBL_HAS_INFINITY__ 1
#define __LFRACT_MIN__ (-0.5LR-0.5LR)
#define __HA_IBIT__ 8
#define __FLT32_DIG__ 6
#define __TQ_IBIT__ 0
#define __FLT_EPSILON__ 1.1920928955078125e-7F
#define __APCS_32__ 1
#define __SHRT_WIDTH__ 16
#define __USFRACT_IBIT__ 0
#define __LDBL_MIN__ 2.2250738585072014e-308L
#define __FRACT_MIN__ (-0.5R-0.5R)
#define __DEC32_MAX__ 9.999999E96DF
#define __DA_IBIT__ 32
#define __ARM_SIZEOF_MINIMAL_ENUM 1
#define __FLT32X_HAS_INFINITY__ 1
#define __INT32_MAX__ 0x7fffffffL
#define __UQQ_FBIT__ 8
#define __INT_WIDTH__ 32
#define __SIZEOF_LONG__ 4
#define __UACCUM_MAX__ 0XFFFFFFFFP-16UK
#define __UINT16_C(c) c
#define __PTRDIFF_WIDTH__ 32
#define __DECIMAL_DIG__ 17
#define __LFRACT_EPSILON__ 0x1P-31LR
#define __FLT64_EPSILON__ 2.2204460492503131e-16F64
#define __ULFRACT_MIN__ 0.0ULR
#define __INTMAX_WIDTH__ 64
#define __has_include_next(STR) __has_include_next__(STR)
#define __LDBL_HAS_QUIET_NAN__ 1
#define __ULACCUM_IBIT__ 32
#define __FLT64_MANT_DIG__ 53
#define __UACCUM_EPSILON__ 0x1P-16UK
#define __GNUC__ 7
#define __ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK
#define __HQ_IBIT__ 0
#define __FLT_HAS_DENORM__ 1
#define __SIZEOF_LONG_DOUBLE__ 8
#define __BIGGEST_ALIGNMENT__ 8
#define __FLT64_MAX_10_EXP__ 308
#define __GNUC_STDC_INLINE__ 1
#define __DQ_IBIT__ 0
#define __DBL_MAX__ ((double)1.7976931348623157e+308L)
#define __ULFRACT_IBIT__ 0
#define __INT_FAST32_MAX__ 0x7fffffff
#define __DBL_HAS_INFINITY__ 1
#define __ACCUM_IBIT__ 16
#define __DEC32_MIN_EXP__ (-94)
#define __INTPTR_WIDTH__ 32
#define __LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK
#define __FLT32X_HAS_DENORM__ 1
#define __INT_FAST16_TYPE__ int
#define __LDBL_HAS_DENORM__ 1
#define __ARM_FEATURE_LDREX 15
#define __DEC128_MAX__ 9.999999999999999999999999999999999E6144DL
#define __INT_LEAST32_MAX__ 0x7fffffffL
#define __ARM_PCS 1
#define __DEC32_MIN__ 1E-95DF
#define __ACCUM_MAX__ 0X7FFFFFFFP-15K
#define __DBL_MAX_EXP__ 1024
#define __USACCUM_EPSILON__ 0x1P-8UHK
#define __WCHAR_WIDTH__ 32
#define __FLT32_MAX__ 3.4028234663852886e+38F32
#define __DEC128_EPSILON__ 1E-33DL
#define __SFRACT_MAX__ 0X7FP-7HR
#define __FRACT_IBIT__ 0
#define __PTRDIFF_MAX__ 0x7fffffff
#define __UACCUM_MIN__ 0.0UK
#define __UACCUM_IBIT__ 16
#define __FLT32_HAS_QUIET_NAN__ 1
#define __LONG_LONG_MAX__ 0x7fffffffffffffffLL
#define __SIZEOF_SIZE_T__ 4
#define __ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK
#define __SIZEOF_WINT_T__ 4
#define __LONG_LONG_WIDTH__ 64
#define __FLT32_MAX_EXP__ 128
#define __SA_IBIT__ 16
#define __ULLACCUM_MIN__ 0.0ULLK
#define __GXX_ABI_VERSION 1011
#define __UTA_FBIT__ 64
#define __FLT_MIN_EXP__ (-125)
#define __USFRACT_MAX__ 0XFFP-8UHR
#define __UFRACT_IBIT__ 0
#define __ARM_FEATURE_QBIT 1
#define __INT_FAST64_TYPE__ long long int
#define __FLT64_DENORM_MIN__ 4.9406564584124654e-324F64
#define __DBL_MIN__ ((double)2.2250738585072014e-308L)
#define __FLT32X_EPSILON__ 2.2204460492503131e-16F32x
#define __FLT64_MIN_EXP__ (-1021)
#define __LACCUM_MIN__ (-0X1P31LK-0X1P31LK)
#define __ULLACCUM_FBIT__ 32
#define __GXX_TYPEINFO_EQUALITY_INLINE 0
#define __FLT64_MIN_10_EXP__ (-307)
#define __ULLFRACT_EPSILON__ 0x1P-64ULLR
#define __USES_INITFINI__ 1
#define __DEC128_MIN__ 1E-6143DL
#define __REGISTER_PREFIX__
#define __UINT16_MAX__ 0xffff
#define __DBL_HAS_DENORM__ 1
#define __ACCUM_MIN__ (-0X1P15K-0X1P15K)
#define __SQ_IBIT__ 0
#define __FLT32_MIN__ 1.1754943508222875e-38F32
#define __UINT8_TYPE__ unsigned char
#define __UHA_FBIT__ 8
#define __SFRACT_MIN__ (-0.5HR-0.5HR)
#define __UTQ_FBIT__ 128
#define __FLT_MANT_DIG__ 24
#define __LDBL_DECIMAL_DIG__ 17
#define __VERSION__ "7.2.1 20170904 (release) [ARM/embedded-7-branch revision 255204]"
#define __UINT64_C(c) c ## ULL
#define __ULLFRACT_FBIT__ 64
#define __FRACT_EPSILON__ 0x1P-15R
#define __ULACCUM_MIN__ 0.0ULK
#define __UDA_FBIT__ 32
#define __LLACCUM_EPSILON__ 0x1P-31LLK
#define __GCC_ATOMIC_INT_LOCK_FREE 2
#define __FLT32_MANT_DIG__ 24
#define __FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__
#define __USFRACT_MIN__ 0.0UHR
#define __UQQ_IBIT__ 0
#define __ARM_NEON__ 1
#define __SCHAR_WIDTH__ 8
#define __INT32_C(c) c ## L
#define __DEC64_EPSILON__ 1E-15DD
#define __ORDER_PDP_ENDIAN__ 3412
#define __DEC128_MIN_EXP__ (-6142)
#define __UHQ_FBIT__ 16
#define __LLACCUM_FBIT__ 31
#define __FLT32_MAX_10_EXP__ 38
#define __INT_FAST32_TYPE__ int
#define __UINT_LEAST16_TYPE__ short unsigned int
#define __INT16_MAX__ 0x7fff
#define __SIZE_TYPE__ unsigned int
#define __UINT64_MAX__ 0xffffffffffffffffULL
#define __UDQ_FBIT__ 64
#define __INT8_TYPE__ signed char
#define __ELF__ 1
#define __ULFRACT_EPSILON__ 0x1P-32ULR
#define __LLFRACT_FBIT__ 63
#define __FLT_RADIX__ 2
#define __INT_LEAST16_TYPE__ short int
#define __ARM_ARCH_PROFILE 65
#define __LDBL_EPSILON__ 2.2204460492503131e-16L
#define __UINTMAX_C(c) c ## ULL
#define __SACCUM_MAX__ 0X7FFFP-7HK
#define __SIG_ATOMIC_MAX__ 0x7fffffff
#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
#define __VFP_FP__ 1
#define __SIZEOF_PTRDIFF_T__ 4
#define __FLT32X_MANT_DIG__ 53
#define __LACCUM_EPSILON__ 0x1P-31LK
#define __FLT32X_MIN_EXP__ (-1021)
#define __DEC32_SUBNORMAL_MIN__ 0.000001E-95DF
#define __INT_FAST16_MAX__ 0x7fffffff
#define __FLT64_DIG__ 15
#define __UINT_FAST32_MAX__ 0xffffffffU
#define __UINT_LEAST64_TYPE__ long long unsigned int
#define __USACCUM_MAX__ 0XFFFFP-8UHK
#define __SFRACT_EPSILON__ 0x1P-7HR
#define __FLT_HAS_QUIET_NAN__ 1
#define __FLT_MAX_10_EXP__ 38
#define __LONG_MAX__ 0x7fffffffL
#define __DEC128_SUBNORMAL_MIN__ 0.000000000000000000000000000000001E-6143DL
#define __FLT_HAS_INFINITY__ 1
#define __USA_FBIT__ 16
#define __UINT_FAST16_TYPE__ unsigned int
#define __DEC64_MAX__ 9.999999999999999E384DD
#define __ARM_32BIT_STATE 1
#define __INT_FAST32_WIDTH__ 32
#define __CHAR16_TYPE__ short unsigned int
#define __PRAGMA_REDEFINE_EXTNAME 1
#define __SIZE_WIDTH__ 32
#define __INT_LEAST16_MAX__ 0x7fff
#define __DEC64_MANT_DIG__ 16
#define __INT64_MAX__ 0x7fffffffffffffffLL
#define __UINT_LEAST32_MAX__ 0xffffffffUL
#define __SACCUM_FBIT__ 7
#define __FLT32_DENORM_MIN__ 1.4012984643248171e-45F32
#define __GCC_ATOMIC_LONG_LOCK_FREE 2
#define __SIG_ATOMIC_WIDTH__ 32
#define __INT_LEAST64_TYPE__ long long int
#define __ARM_FEATURE_CLZ 1
#define __INT16_TYPE__ short int
#define __INT_LEAST8_TYPE__ signed char
#define __SQ_FBIT__ 31
#define __DEC32_MAX_EXP__ 97
#define __ARM_ARCH_ISA_THUMB 2
#define __INT_FAST8_MAX__ 0x7fffffff
#define __ARM_ARCH 7
#define __INTPTR_MAX__ 0x7fffffff
#define __QQ_FBIT__ 7
#define __UTA_IBIT__ 64
#define __FLT64_HAS_QUIET_NAN__ 1
#define __FLT32_MIN_10_EXP__ (-37)
#define __FLT32X_DIG__ 15
#define __LDBL_MANT_DIG__ 53
#define __SFRACT_FBIT__ 7
#define __SACCUM_MIN__ (-0X1P7HK-0X1P7HK)
#define __DBL_HAS_QUIET_NAN__ 1
#define __FLT64_HAS_INFINITY__ 1
#define __SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)
#define __INTPTR_TYPE__ int
#define __UINT16_TYPE__ short unsigned int
#define __WCHAR_TYPE__ unsigned int
#define __SIZEOF_FLOAT__ 4
#define __USQ_FBIT__ 32
#define __UINTPTR_MAX__ 0xffffffffU
#define __INT_FAST64_WIDTH__ 64
#define __DEC64_MIN_EXP__ (-382)
#define __ULLACCUM_IBIT__ 32
#define __FLT32_DECIMAL_DIG__ 9
#define __INT_FAST64_MAX__ 0x7fffffffffffffffLL
#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
#define __FLT_DIG__ 6
#define __FLT32_HAS_INFINITY__ 1
#define __UINT_FAST64_TYPE__ long long unsigned int
#define __INT_MAX__ 0x7fffffff
#define __LACCUM_FBIT__ 31
#define __USACCUM_MIN__ 0.0UHK
#define __UHA_IBIT__ 8
#define __INT64_TYPE__ long long int
#define __FLT_MAX_EXP__ 128
#define __UTQ_IBIT__ 0
#define __DBL_MANT_DIG__ 53
#define __INT_LEAST64_MAX__ 0x7fffffffffffffffLL
#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
#define __DEC64_MIN__ 1E-383DD
#define __WINT_TYPE__ unsigned int
#define __UINT_LEAST32_TYPE__ long unsigned int
#define __SIZEOF_SHORT__ 2
#define __ULLFRACT_IBIT__ 0
#define __LDBL_MIN_EXP__ (-1021)
#define __arm__ 1
#define __FLT64_MAX__ 1.7976931348623157e+308F64
#define __UDA_IBIT__ 32
#define __WINT_WIDTH__ 32
#define __INT_LEAST8_MAX__ 0x7f
#define __FLT32X_MAX_10_EXP__ 308
#define __LFRACT_FBIT__ 31
#define __ARM_ARCH_7A__ 1
#define __LDBL_MAX_10_EXP__ 308
#define __ATOMIC_RELAXED 0
#define __DBL_EPSILON__ ((double)2.2204460492503131e-16L)
#define __ARM_FEATURE_SIMD32 1
#define __UINT8_C(c) c
#define __FLT64_MAX_EXP__ 1024
#define __INT_LEAST32_TYPE__ long int
#define __SIZEOF_WCHAR_T__ 4
#define __UINT64_TYPE__ long long unsigned int
#define __OPTIMIZE_SIZE__ 1
#define __ARM_NEON 1
#define __LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLR
#define __TQ_FBIT__ 127
#define __INT_FAST8_TYPE__ int
#define __ULLACCUM_EPSILON__ 0x1P-32ULLK
#define __UHQ_IBIT__ 0
#define __ARM_FEATURE_COPROC 15
#define __LLACCUM_IBIT__ 32
#define __FLT64_HAS_DENORM__ 1
#define __FLT32_EPSILON__ 1.1920928955078125e-7F32
#define __DBL_DECIMAL_DIG__ 17
#define __INT_FAST8_WIDTH__ 32
#define __DEC_EVAL_METHOD__ 2
#define __FLT32X_MAX__ 1.7976931348623157e+308F32x
#define __TA_FBIT__ 63
#define __UDQ_IBIT__ 0
#define __ORDER_BIG_ENDIAN__ 4321
#define __ACCUM_EPSILON__ 0x1P-15K
#define __UINT32_C(c) c ## UL
#define __INTMAX_MAX__ 0x7fffffffffffffffLL
#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
#define __FLT_DENORM_MIN__ 1.4012984643248171e-45F
#define __LLFRACT_IBIT__ 0
#define __INT8_MAX__ 0x7f
#define __LONG_WIDTH__ 32
#define __UINT_FAST32_TYPE__ unsigned int
#define __CHAR32_TYPE__ long unsigned int
#define __FLT_MAX__ 3.4028234663852886e+38F
#define __USACCUM_FBIT__ 8
#define __INT32_TYPE__ long int
#define __SIZEOF_DOUBLE__ 8
#define __FLT_MIN_10_EXP__ (-37)
#define __UFRACT_EPSILON__ 0x1P-16UR
#define __FLT64_MIN__ 2.2250738585072014e-308F64
#define __INT_LEAST32_WIDTH__ 32
#define __INTMAX_TYPE__ long long int
#define __DEC128_MAX_EXP__ 6145
#define __FLT32X_HAS_QUIET_NAN__ 1
#define __ATOMIC_CONSUME 1
#define __GNUC_MINOR__ 2
#define __INT_FAST16_WIDTH__ 32
#define __UINTMAX_MAX__ 0xffffffffffffffffULL
#define __DEC32_MANT_DIG__ 7
#define __FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32x
#define __HA_FBIT__ 7
#define __DBL_MAX_10_EXP__ 308
#define __LDBL_DENORM_MIN__ 4.9406564584124654e-324L
#define __INT16_C(c) c
#define __STDC__ 1
#define __PTRDIFF_TYPE__ int
#define __LLFRACT_MIN__ (-0.5LLR-0.5LLR)
#define __ATOMIC_SEQ_CST 5
#define __DA_FBIT__ 31
#define __UINT32_TYPE__ long unsigned int
#define __FLT32X_MIN_10_EXP__ (-307)
#define __UINTPTR_TYPE__ unsigned int
#define __USA_IBIT__ 16
#define __DEC64_SUBNORMAL_MIN__ 0.000000000000001E-383DD
#define __ARM_EABI__ 1
#define __DEC128_MANT_DIG__ 34
#define __LDBL_MIN_10_EXP__ (-307)
#define __SIZEOF_LONG_LONG__ 8
#define __ULACCUM_EPSILON__ 0x1P-32ULK
#define __SACCUM_IBIT__ 8
#define __GCC_ATOMIC_LLONG_LOCK_FREE 2
#define __FLT32X_MIN__ 2.2250738585072014e-308F32x
#define __LDBL_DIG__ 15
#define __FLT_DECIMAL_DIG__ 9
#define __UINT_FAST16_MAX__ 0xffffffffU
#define __GCC_ATOMIC_SHORT_LOCK_FREE 2
#define __INT_LEAST64_WIDTH__ 64
#define __ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLR
#define __UINT_FAST8_TYPE__ unsigned int
#define __USFRACT_EPSILON__ 0x1P-8UHR
#define __ULACCUM_FBIT__ 32
#define __ARM_FEATURE_DSP 1
#define __QQ_IBIT__ 0
#define __ATOMIC_ACQ_REL 4
#define __ATOMIC_RELEASE 3

Differentiating Cortex-A s using MIDR register

https://github.com/torvalds/linux/blob/master/arch/arm/mm/proc-v7.S

SSH Testing using WolfSSL

1) Download WolfSSH and WolfSSL from Download page of WolfSSL homepage. Just user information is given and download was possible.

2) Place WolfSSL and WolfSSH in the same parent directory as mentioned in the ReadMe of IDE\Win folder and copy the user_settings.h to WolfSSL.

3) Build WolfSSL Library by selecting “wolfssl64.sln” from the root directory of WolfSSL in Visual Studio.

4) Then build the WolfSSH from IDE\WIN.

5) Then execute the Echoserver and Client programs. User name and password is in the server source file.

RFCs:
https://www.ssh.com/ssh/protocol/

https://www.samtec.com/jp/standards/jtag

JTAG 20 pin dimensions

ARM Standard JTAG Connector (20-pins, 0.10")

The header (e.g. a Samtec TST-110-01-L-D) is a 20-Pin, 0.10" (2.54 mm) pitch connector with these these dimensions: 1.3" x 0.365" (33 mm x 9.27mm).

https://www.digikey.com/product-detail/en/samtec-inc/TST-110-01-L-D/SAM10837-ND/2685837
-----

FTSH-110-01-L-DV-K

It's dimensions are: 0.50" x 0.188" (12.70mm x 4.78mm).


https://www.samtec.com/products/ftsh-110-01-l-dv-k

Connectors

http://www.keil.com/support/man/docs/jlink/jLink_connectors.htm

What's the difference between versions 1 and 2 of the SSH protocol?

http://www.snailbook.com/faq/ssh-1-vs-2.auto.html

PIC32 microAptive core

https://www.mips.com/products/aptiv/microaptiv/

First follow up microAptive UP core which has MMU.

Poring Features:

CPU operating modes: 

the operating modes (kernel, user, and debug). This is controlled by System Control Coprocessor (CP0).

Howto switch between the modes?

5.8.17 Execution Exception — System Call
The system call exception is one of the execution exceptions. All of these exceptions have the same priority. A system
call exception occurs when a SYSCALL instruction is executed.
Cause Register ExcCode Value:
Sys
Additional State Saved:
None
Entry Vector Used:
General exception vector (offset 0x180)

Table 6.28 Cause Register ExcCode Field
Exception Code Value
8 16#08 Sys Syscall exception


http://www.it.uu.se/education/course/homepage/os/vt18/module-1/assignment/
When an exception or interrupt occurs, the address of the program counter of the currently executing program is automatically saved to the EPC register in coprocessor 0 and control is transferred from user mode to kernel mode.

https://github.com/uu-os-2018/module-1

Exceptions. Any supervisor calls?

Yes. Syscall instruction is available.

Volatile and Non-volatile registers

https://courses.cs.washington.edu/courses/cse410/09sp/examples/MIPSCallingConventionsSummary.pdf

R0~R31 registers. Specified as $0~$31

Volatile:
R0 → Always 0. ($0)
R1 → $at → Assembler Temporary ($at )
R2, R3 → Volatile. Return value ($v0-$v1)
R4~R7 → Volatile. Arguments ($a0-$a3)
R8~R15, R24, R25 →  The Temporary Registers.Volatile. ($t0-$t9)
R26-R27 →The Kernel Reserved registers. DO NOT USE. ($k0-$k1)

Non-Volatile:
R16~R23 → Non-volatile. Saved Registers. ($s0-$s7)
R28 → Globals Pointer ($gp)
R29 → Stack Pointer ($sp)

R30 → Frame pointer ($fp or $s8)
R31 → Holds the return address for a function call.

Instructions are like ARM only.

stack frame is always a multiple of 8.

MIPS Instruction Set Quick Reference:
https://www2.cs.duke.edu/courses/fall13/compsci250/MIPS32_QRC.pdf

PIC32MZ DA

PIC32MZ2064DAA176
https://www.microchip.com/wwwproducts/en/PIC32MZ2064DAA176

Features:

• 200 MHz/330 DMIPS, MIPS32 microAptiv core
• Dual Panel Flash for live update support
• 12-bit, 18 MSPS, 45-channel ADC module
• Memory Management Unit for optimum embedded OS execution
• microMIPS mode for up to 35% code compression
• CAN, UART, I2C, PMP, EBI, SQI & Analog Comparators

----

Part Family

PIC32MZDA

Max CPU Speed MHz

200

Program Memory Size (KB)

2048

SRAM (KB)

640

SDIO/SD-CARD/eMMC

1

Temperature Range (C)

-40 to 85

Operating Voltage Range (V)

2.2 to 3.6

Graphics Controller/GPU

Yes

Direct Memory Access Channels

8

SPI

6

I2C

5

CODEC Interface (I2S,AC97)

Yes

Peripheral Pin Select / Pin Muxing

Yes

CTMU test

Yes

Ethernet

10/100 Base-TX Mac

Number of Ethernet Ports

1

Number of USB Modules

1

USB Interface

High Speed

Number of CAN modules

2

Type of CAN module

CAN

ADC Input

45

Max ADC Resolution (Bits)

12

Max ADC Sampling Rate (ksps)

18000

Input Capture

9

Standalone Output Compare/Standard PWM

9

Max 16-bit Digital Timers

9

Parallel Port

PMP

Number of Comparators

2

Internal Oscillator

8 MHz, 32 KHz

Hardware RTCC/RTC

Yes

Max I/O Pins

120

Pincount

176

Serial Quad Interface

Ye

Creating a "Hello World" Application Using the MPLAB Harmony Configurator (MHC)

http://ww1.microchip.com/downloads/en/DeviceDoc/90003177A.pdf

Summary

Consider using the PIC32MZ2064DAK176 for new designs.

PIC32MZ DA series offers MPU like performance with ease of design of an MCU for GUI designs with it’s 2MB Flash and 640KB of SRAM, available on-chip 32MB or 128MB externally addressable DDR2 DRAM, integrated Graphics Controller, Graphics Processor, 200 MHz speed, 12-bit 18 MSPS ADC module with up to 45 analog inputs, CAN and HS USB.

Please consider this device PIC32MZ2064DAK176

Additional Features

Key Features
• 200 MHz/330 DMIPS, MIPS32 microAptiv core
• Dual Panel Flash for live update support
• 12-bit, 18 MSPS, 45-channel ADC module
• Memory Management Unit for optimum embedded OS execution
• microMIPS mode for up to 35% code compression
• CAN, UART, I2C, PMP, EBI, SQI & Analog Comparators
• SPI/I2S interfaces for audio processing and playback
• Hi-Speed USB Device/Host/OTG
• 10/100 Mbps Ethernet MAC with MII and RMII interface
• Advanced Memory Protection
  • Peripheral and memory region access control
• Temperature Range - 40°C to 85°C, - 40°C to 105°C (planned)
Microcontroller Features
• Operating voltage range of 2.3V to 3.6V
• 2MB Flash memory (plus an additional 160 KB of Boot Flash)
• 640KB SRAM memory
• microMIPS mode for up to 35% smaller code size
• DSP-enhanced core:
  • Four 64-bit accumulators
  • Single-cylce MAC, saturating and fractional math
  • IEEE 754-compliant
• Code-efficient (C and Assembly) architecture
Power Management
• Various power management options for extreme power reduction (VBAT, Deep Sleep, Sleep and Idle)
• Deep Sleep current: < 1µA (typical)
• Integrated POR and BOR
• Programmable High/Low-Voltage Detect (HLVD) on VDDIO and High-Voltage Detect (HVD) on VDDR1V8
Clock Management
• Programmable PLLs and oscillator clock sources
• Dedicated PLL for DDR2
• Fail-Safe Clock Monitor
• Independent Watchdog and Deadman Timers
• Fast wake-up and start-up
Peripheral Features
• 50 MHz SD/SDIO/eMMC bus interface
• 50 MHz External Bus Interface (EBI)
• 80 MHz Serial Quad Interface (SQI)
• Peripheral Pin Select (PPS) functionality to enable function remap
• Up to 8 channels of hardware DMA with automatic data size detection
• Six UART modules (25 Mbps): Supports LIN 1.2 and IrDA protocols
• Two CAN modules 2.0B Active with DeviceNet addressing support
• Six 4-wire SPI modules (80 Mbps)
• SQI configurable as an additional SPI module (50 MHz)
• Five I2C modules (up to 1 Mbaud) with SMBus support
• Parallel Master Port (PMP)
• Hardware Real-Time Clock and Calendar (RTCC) module
• Nine 16-bit Timers/Counters (four 16-bit pairs combine to create four 32-bit timers)
• Nine Input Capture (IC) and Nine Output Compare(OC)/PWM outputs
    Graphics Features
• 3-layer Graphics Controller with up to 24-bit color support
• High-performance 2D Graphics Processing Unit (GPU)
Audio Features
• Audio data communication: I2S, LJ, RJ, USB
• Audio data control interface: SPI and I2C™
• Audio data master clock: Fractional clock frequencies with USB synchronization
Advanced Analog Features
• 12-bit ADC Module:
• 18Msps rate with six Sample and Hold (S&H) circuits (five dedicated and one shared)
• Up to 45 analog inputs
• Can operate during sleep and idle modes
• Multiple trigger sources
• Six digital comparators and six digital filters
• Two comparators with 32 programmable voltage references
• Temperature sensor with ±2°C accuracy
• Charge Time Measurement Unit (CTMU)
Qualification and Class B Support
• AEC-Q100 REVG (Grade 2 -40oC to +105oC) (Planned)
• Class B Safety Library, IEC 60730
• Back-up internal oscillator
Debugger Development Support
• In-circuit and in-application programming
• 4-wire MIPS® Enhanced JTAG interface
• Unlimited program and 12 complex data breakpoints
• IEEE 1149.2-compatible (JTAG) boundary scan
• Non-intrusive hardware-based instruction trace
Integrated Software Libraries and Tools
• MPLAB Harmony – PIC32 software development framework
• C/C++ compiler with native DSP/fractional and FPU support
• TCP/IP, USB, Graphics, and mTouch middleware
• MFi, Android, and Bluetooth audio frameworks
• RTOS Kernels, Express Logic ThreadX FreeRTOS, OPENRTOS, Micriµm, µC/OS and SEGGER embOS

Research Papers

https://www.researchgate.net/publication/331460321_Energy-Efficient_Intra-Task_DVFS_Scheduling_Using_Linear_Programming_Formulation/download

Income returns deadlines

Creating NIOS design

http://scale.engin.brown.edu/classes/EN2911XF12/nios2.pdf

Directly Editing the Makefile
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd02212012_654.html

Nested Interrupts in NIOS

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/n2sw_nii52006.pdf


For the IIC, irq is the IRQ number. Interrupt priority corresponds inversely to
the IRQ number. Therefore, IRQ0 represents the highest priority interrupt and
IRQ31 is the lowest.

Nested Hardware Interrupts with the Internal Interrupt Controller
To implement nested hardware interrupts with the IIC, use the
alt_irq_interruptible() and alt_irq_non_interruptible() functions to bracket
code in a processor-intensive ISR. The call to alt_irq_interruptible() adjusts the
interrupt mask so that higher-priority interrupts can take control from the running
ISR. When your ISR calls alt_irq_non_interruptible(), the interrupt mask is
returned to its previous state.

If you use a separate exception stack with the IIC, you cannot nest hardware
interrupts. For more information about separate exception stacks, refer to “Use a
Separate Exception Stack”.

--
Table 8–1. Enhanced HAL Interrupt API Functions
Function Name Implemented By
alt_ic_isr_register() Interrupt controller driver (1)
alt_ic_irq_enable() Interrupt controller driver (1)
alt_ic_irq_disable() Interrupt controller driver (1)
alt_ic_irq_enabled() Interrupt controller driver (1)
alt_irq_disable_all() HAL
alt_irq_enable_all() HAL
alt_irq_enabled() HAL

The Legacy HAL Interrupt API The legacy HAL interrupt API defines the following functions to manage hardware interrupt processing:
■ alt_irq_register()
■ alt_irq_disable()
■ alt_irq_enable()
■ alt_irq_disable_all()
■ alt_irq_enable_all()
■ alt_irq_interruptible()
■ alt_irq_non_interruptible()
■ alt_irq_enabled()
--

https://forums.intel.com/s/question/0D50P00003yyKIXSA2/enhanced-interrupt-api?language=en_US
https://forums.intel.com/s/question/0D50P00003yyMw5SAE/why-i-can-not-find-the-altirqenable-function-in-halsrceclipse-for-niosii?language=en_US



alt_putstr(char *) is function to print in the NIOS console.

If download failed without any reason, please refresh connections few times and make sure the Blaster II connection is available and Click APPLY and then Debug.

Calling Standard Library/BSP functions, Re-entrant and Stack Usage

If a task is specified as re-entrant, mkreent() function is called to allocate space for global and task specific data pointed by _impure pointer. Otherwise, just 4 bytes are allocated (IMPURE variable) just to store the _impure pointer alone.

https://www.segger.com/downloads/embos/UM01035_embOS_NIOS2.pdf

5.3 Reentrancy

ARM Learning

https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides?_ga=2.67783889.1301034120.1560212277-687559717.1455694541

https://pages.arm.com/Perf-analysis-for-embedded-deep-learning-typ.html?aliId=eyJpIjoiaXRBSStJdGJjVjVRR3Z6UyIsInQiOiJXZjMyNWRaNVByWlF4SXByb3RoMmVBPT0ifQ%253D%253D

ML7304 supports only Little Endian

http://www.lapis-semi.com/jp/data/user's%20manual-file_db/telecom/FJUL7304-0X2IPFULL-F83-1.0.pdf

【注意】 CPU のアーキテクチャではビッグエンディアンあるいはリトルエンディアンのいずれかを選択してメモリ中のワードを扱 うことができますが、本 LSI ではリトルエンディアンに固定されています。

IoT Journey

IoT Eclipse PPT
https://www.slideshare.net/IanSkerrett/3-software-stacks-for-iot-solutions

MQTT Client library for Windows C downloaded:

https://projects.eclipse.org/projects/iot.paho/downloads

Details on MQTT

http://www.steves-internet-guide.com/mqtt/

Moaquito Broker needs to be installed to pass the messages to/from MQTT client.

Simple MQTT client here: SRC/APPS/MQTT
http://download.savannah.nongnu.org/releases/lwip/
https://www.nongnu.org/lwip/2_0_x/group__mqtt.html

Comparison of MQTT implementations
https://en.wikipedia.org/wiki/Comparison_of_MQTT_implementations

Echo Tool

2. From the command window, type echotool 192.168.0.102 /p tcp /r 7 /d hello
NOTE: The echotool.exe application can be found here https://github.com/PavelBansky/EchoTool

To edit photos online

https://www110.lunapic.com/editor/

Draw -> Paint bucket tool -> Select the image in clipboard -> Select clipboard in Pattern -> click the color to be filled in.

GNU GCC linker - Ordering a particular object file

MEMORY {
    SDRAM_1   (rwx) : ORIGIN = 0x4c000000, LENGTH = 0x00100000
    SDRAM_2   (rw)  : ORIGIN = 0x4c100000  LENGTH = 0x00200000
    SPIFLASH  (rw)  : ORIGIN = 0x30000000  LENGTH = 0x000FFFFF
}

ENTRY(__RESET)
EXTERN(SPIBOOT)

SECTIONS {

    .rom : {
        . = 0x00000000;
        * (.boot_param)
        PROVIDE(__rom_code = .);
    } > SPIFLASH

    .text : AT ( __rom_code ) {
        PROVIDE(__ro_start__ = .);
        . = 0x00000000;
          * (.vectors)

        . = 0x00000200;
          * (INIT)
          *aprzt0a.o (.text .text.*)
          * (.text .text.*)
          * (.rodata .rodata.*)
        PROVIDE(__ro_end__ = .);
    } > SDRAM_1

EWARM Link guide

https://www.iar.com/globalassets/2/ew_ilinkguide.jpn_20131006.pdf

If you refer SFE(.text) or SFB(.text), the linker does not obey to your rules in your linker definition file and it just clubs all together to find the end and start of .text section. Use block instead as follows:

define block TEXT with fixed order { rw code object mpu7r.o, rw code object rskrat1.o, rw code };
define block TEXT_init with fixed order { ro code object mpu7r.o, ro code object rskrat1.o, ro code };

----
Even Text and .rodata can be split as follows:
define block TEXT { ro code };
define block RODATA { readonly };

RZ/A2M SDRAM Initialization

In the Board manual itself:

https://www.renesas.com/jp/ja/doc/products/tool/doc/004/r20ut4398jj0100-rza2m.pdf

English
https://www.renesas.com/kr/en/doc/products/tool/doc/004/r20ut4398ej0100-rza2m.pdf

MicroChip PHYs

 * Giga phys: ksz9021, ksz9031, ksz9131

 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
 *    ksz8021, ksz8031, ksz8051,
 *    ksz8081, ksz8091,
 *    ksz8061,

 * Switch : ksz8873, ksz886x
 * ksz9477s

I had said that Marvell 88E1152 was similar to 88E111x and EEE erratta needs to be added. But, it was wrong. The registers for RGMII Delay and RGMII Copper mode settings were completely different and the default setup supports both on 88E1152. I removed any 88E1152 specific setting.

RZ/N1D Ethernets

RZ/N1 Further clarity

RZ/N1D/S/L has Double/Single/Zero cores of Cortex-A7.
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzn/rzn1.html
So, better to have separate start-ups for each.

Please refer to “CoreLink™ GIC-400 Generic Interrupt Controller Technical Reference Manual” on Arm website.

Clocks got as follows:

Timer clock is got from CNTFRQ register as follows:
        mrc     p15, #0, r0, c14, c0, #0

How is it derived is not known yet. Other serial and Ethernet are as follows:

GPIO configuration after main

GPIO programming
https://deepbluembedded.com/input-output-io-ports-gpio-pins/

PowerPoint Method
http://www.powerpoint-study.com/index.html
http://www.inden.ne.jp/dekiroute/archives/1961

RZ/N1D Ethernet Setup concepts

RGMII/RMII Converters (All are Ethernet Accessory only. Differs in Converters or Switch Ports)

rzn1_rgmii_rmii_conv_setup(conv_number, IF type, shoudRMIIrefclkOut?) {
1) CONVCTRL register setup → set static IF type and Clock output bits of CONVCTRL
    set up of RGMII? or RMII? or MII? bit
    if RMII, set CONVCTRL_REF_CLK_OUT bit

    rzn1_rgmii_rmii_conv_speed(conv number, full_duplex?, speed?)→set dynamic speed and duplex bits of CONVCTRL
    a) set 1000MBPS? 100MBPS? 10MBPS? speed bit (Only if not MII interface)
    b) if full duplex, set FULL_DUPLEX bit

    rzn1_rin_switchcore_setup() → Only switch ports (see the Converter-Switch port mapping below)
    i) set 10M or/and 1000M bits of SWCTRL register according to speed.
    ii) set the Duplex bit of SWDUPC register.
      (It has been written in manual that these fields of SWCTRL and SWDUPC can be set to 0 and instead COMMAND_CONFIG_P[n] can used to set the actual values.)

2) reset using CONVRST register
    clear PHYRST bit
    wait for 1ms
    set PHYRST bit
}

Ethernet Ports→Converters→PHYs→External Connectors. Consider, where and all PHY is coming there needs to be a converter. So, total 5 converters. One is GMAC1 directly exposed out and other four are for external ports of A5PSW switch.

Converter Mapping:
Converter 0 → Directly exposed GMAC1
                         (GMAC2<->Switch Port 4 is management port that does not have converter either)
Converter 1 → Switch Port 3
Converter 2 → Switch Port 2
Converter 3 → Switch Port 1
Converter 4 → Switch Port 0

The above converters are set as follows in U-boot
Converter 0 → RGMII, no RMII clock output
Converter 1 → RGMII, no RMII clock output (Switch Port 3)
Converter 2 → RGMII, no RMII clock output (Switch Port 2)
Converter 3 → MII, RMII clock output (Switch Port 1)
Converter 4 → MII, RMII clock output (Switch Port 0)

                                                                                                                                                  

Now, come to actual A5PSW setting..

rzn1_switch_setup_port_speed(port, speed, eanble) {

    1) rzn1_mt5pt_switch_setup_port_speed(port, speed)
        if 1000M, set MBPS_1000 bit of MAC_CMD_CFGn(port) register

    2) if (enable), rzn1_mt5pt_switch_enable_port(port)
        set AUTH_PORT_AUTHORIZED bit of AUTH_PORT(port) register
        set PORT_ENA_TXRX bit of PORT_ENA register
}

From Setup point of view,
First, set upstream port to fixed 1000M.
    rzn1_switch_setup_port_speed(4, 1000M, 1);
Next, all other ports are setup by link-change callback (phy_adjust_link_notifier).
    for (port = 0; port < 4; port++) {
        rzn1_rgmii_rmii_conv_speed(4 - port, duplex, speed) → Dynamic link speed/duplex setting of CONVCTRL
        rzn1_switch_setup_port_speed(port, speed, enable);
    }

Regarding the PHY address assignment, if PHY address 4/5, it is MII. Otherwise, RGMII.
Look here, U-Boot just selects one external port from the switch, and based on the link speed/duplex of that specific port, it updates the same with all ports.
                                                                                                                                                        

4.4 U-Boot Download and Reference source

4.4.1 Setup

On your host PC, the following command will download the RZ/N1 branch for U-Boot, including all
commit history. Note that it will result in a large download

git clone http://git.denx.de/u-boot.git
cd u-boot

Checkout a branch based on the 2017.01 version:

git checkout -b rzn1 v2017.01

Set the BSP version to according to the release, for example:

BSP_VERSION=v1.5.3

Fetch the RZ/N1 branch and merge it in:

git remote add renesas-rz https://github.com/renesas-rz/rzn1_u-boot.git
git fetch --tags renesas-rz
git merge rzn1-public-$BSP_VERSION

4.4.2 Build

To setup the configuration for the Renesas RZ/N1D-DB Board, run:

make rzn1d400-db_config

To setup the configuration for the Renesas RZ/N1S-DB Board, run:

make rzn1s324-db_config

To setup the configuration for the Renesas RZ/N1S IO-Link Board, run:

make rzn1s-io-link_config

To setup the configuration for the Renesas RZ/N1L-DB Board, run:

make rzn1l-db_config

To build U-Boot, run:

make

Once complete, the Elf image is stored as u-boot. The image is built to execute from internal
SRAM on the RZ/N1 devices, see section 5.2 for details. You can download this file using a
debugger.

                                                                                                                                                   

By default, U-Boot uses the first available network interface. If that interface is down. It will try the
next one. You can set the default network interface to GMAC2, for example, by setting:


setenv ethact dwmac.44002000

Booting of Kernel that supports Advanced 5port Switch

tftp 0x80008000 192.168.1.2:uImage

tftp 0x8ffe0000 192.168.1.2:rzn1d400-db.dtb

bootm 0x80008000 - 0x8ffe0000