PIC32 microAptive core

https://www.mips.com/products/aptiv/microaptiv/

First follow up microAptive UP core which has MMU.

Poring Features:

CPU operating modes: 

the operating modes (kernel, user, and debug). This is controlled by System Control Coprocessor (CP0).

Howto switch between the modes?

5.8.17 Execution Exception — System Call
The system call exception is one of the execution exceptions. All of these exceptions have the same priority. A system
call exception occurs when a SYSCALL instruction is executed.
Cause Register ExcCode Value:
Sys
Additional State Saved:
None
Entry Vector Used:
General exception vector (offset 0x180)

Table 6.28 Cause Register ExcCode Field
Exception Code Value
8 16#08 Sys Syscall exception


http://www.it.uu.se/education/course/homepage/os/vt18/module-1/assignment/
When an exception or interrupt occurs, the address of the program counter of the currently executing program is automatically saved to the EPC register in coprocessor 0 and control is transferred from user mode to kernel mode.

https://github.com/uu-os-2018/module-1

Exceptions. Any supervisor calls?

Yes. Syscall instruction is available.

Volatile and Non-volatile registers

https://courses.cs.washington.edu/courses/cse410/09sp/examples/MIPSCallingConventionsSummary.pdf

R0~R31 registers. Specified as $0~$31

Volatile:
R0 → Always 0. ($0)
R1 → $at → Assembler Temporary ($at )
R2, R3 → Volatile. Return value ($v0-$v1)
R4~R7 → Volatile. Arguments ($a0-$a3)
R8~R15, R24, R25 →  The Temporary Registers.Volatile. ($t0-$t9)
R26-R27 →The Kernel Reserved registers. DO NOT USE. ($k0-$k1)

Non-Volatile:
R16~R23 → Non-volatile. Saved Registers. ($s0-$s7)
R28 → Globals Pointer ($gp)
R29 → Stack Pointer ($sp)

R30 → Frame pointer ($fp or $s8)
R31 → Holds the return address for a function call.

Instructions are like ARM only.

stack frame is always a multiple of 8.

MIPS Instruction Set Quick Reference:
https://www2.cs.duke.edu/courses/fall13/compsci250/MIPS32_QRC.pdf