MEMORY {
SDRAM_1 (rwx) : ORIGIN = 0x4c000000, LENGTH = 0x00100000
SDRAM_2 (rw) : ORIGIN = 0x4c100000 LENGTH = 0x00200000
SPIFLASH (rw) : ORIGIN = 0x30000000 LENGTH = 0x000FFFFF
}
ENTRY(__RESET)
EXTERN(SPIBOOT)
SECTIONS {
.rom : {
. = 0x00000000;
* (.boot_param)
PROVIDE(__rom_code = .);
} > SPIFLASH
.text : AT ( __rom_code ) {
PROVIDE(__ro_start__ = .);
. = 0x00000000;
* (.vectors)
. = 0x00000200;
* (INIT)
*aprzt0a.o (.text .text.*)
* (.text .text.*)
* (.rodata .rodata.*)
PROVIDE(__ro_end__ = .);
} > SDRAM_1
SDRAM_1 (rwx) : ORIGIN = 0x4c000000, LENGTH = 0x00100000
SDRAM_2 (rw) : ORIGIN = 0x4c100000 LENGTH = 0x00200000
SPIFLASH (rw) : ORIGIN = 0x30000000 LENGTH = 0x000FFFFF
}
ENTRY(__RESET)
EXTERN(SPIBOOT)
SECTIONS {
.rom : {
. = 0x00000000;
* (.boot_param)
PROVIDE(__rom_code = .);
} > SPIFLASH
.text : AT ( __rom_code ) {
PROVIDE(__ro_start__ = .);
. = 0x00000000;
* (.vectors)
. = 0x00000200;
* (INIT)
*aprzt0a.o (.text .text.*)
* (.text .text.*)
* (.rodata .rodata.*)
PROVIDE(__ro_end__ = .);
} > SDRAM_1
No comments:
Post a Comment