NTP

NTP Japanese article

http://www.atmarkit.co.jp/ait/articles/1203/15/news121.html

Xilinx AXI Ethernet

http://lxr.free-electrons.com/source/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
http://lxr.free-electrons.com/source/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c#L20


Half-Duplex Mode: When this bit is 1, the transmitter operates in
half-duplex mode. When this bit is 0, the transmitter operates in
full-duplex mode. Only full-duplex is supported so this bit should
always be set to 0.

There is basically difference between Marvell 88E1111S and 88E1011S. But, lanphy.c has 88E1011S settings for 88E1111S. Refer to the following:
https://github.com/Xilinx/u-boot-xlnx/blob/master/drivers/net/phy/marvell.c

88E1111S  Vs 88E1116R
http://svn.dd-wrt.com/browser/src/linux/universal/linux-3.12/drivers/net/phy/marvell.c?rev=22733

Microblaze version tracking

#define __GNUC__ 5

#define __GNUC_MINOR__ 2

#define __GNUC_PATCHLEVEL__ 0

For example,

http://lxr.free-electrons.com/source/include/linux/compiler.h?v=2.4.37

http://www.boost.org/doc/libs/1_61_0/boost/optional/detail/optional_config.hpp

GCC assembler comments style differs based on architecture. For PowerPC and MicroBlaze, it is #. For ARM, it is @.


SDK version GCC version
SDK 2019.1          8.2
SDK 2018.3          7.3
SDK 2018.2          7.2
SDK 2018.1          7.2
SDK 2017.4 6.2
SDK 2017.3 6.2
SDK 2016.4 5.2
SDK 2016.3 5.2
SDK 2016.1 5.2 (Upgraded to)
SDK 2015.4 4.9.2
SDK 2015.3 4.9.2
SDK 2015.1 4.9.2 (Upgraded to)
SDK 2014.1 4.8.3 (Upgraded to)
SDK 14.5/2013.1
EDK14.1 4.6.2


https://www.xilinx.com/support/answers/55776.html


GCC version comparison

https://sourceforge.net/p/stxxl/git/ci/61b7fe42d2ff7ae5157049b720793c380450c6c2/tree/include/stxxl/bits/compat/shared_ptr.h?barediff=e95b9e0556953f21f002d9128de5becbba68b98e

https://gcc.gnu.org/onlinedocs/gcc-4.0.2/cpp/Common-Predefined-Macros.html


Fast Simplex Link (FSL) Interface Description
The Fast Simplex Link bus provides a point-to-point communication channel between an output FIFO and an input FIFO.

Interrupt Level Control By Software


http://google.co.kr/patents/US20050193260

ARM floating license

Start lmtool in Vaio of your user name/download

Assign the IP/8224 in the license manager of DS-5.

LS102A Timer

https://github.com/linaro-swg/u-boot/blob/master/arch/arm/cpu/armv7/ls102xa/timer.c

http://u-boot.10912.n7.nabble.com/PATCH-v6-0-17-arm-ls102xa-Add-Freescale-LS102xA-SoC-and-LS1021AQDS-TWR-board-support-td188615.html

Color code
http://code.metager.de/source/xref/denx/u-boot/arch/arm/cpu/armv7/ls102xa/timer.c


http://www.mit.edu/afs.new/sipb/contrib/linux/drivers/clocksource/arm_arch_timer.c

arm_arch_timer.h
https://kernel.googlesource.com/pub/scm/linux/kernel/git/kishon/linux-phy/+/phy-for-4.9-resolved_v1/include/clocksource/arm_arch_timer.h


Search "sched_clock: ARM arch timer"

Good Linux Cross reference site
http://osxr.org:8080/linux/source/arch/arm/include/asm/arch_timer.h

Linux overall flow
http://www.makelinux.net/books/lkd2/ch10lev1sec5


LS1021A. SGMII
http://lxr.free-electrons.com/source/drivers/net/ethernet/freescale/gianfar.c
http://lxr.free-electrons.com/source/drivers/net/ethernet/freescale/fsl_pq_mdio.c

LPUART
https://searchcode.com/codesearch/view/57817926/

NXP Helpful queries

LS1021A. How to start secondary core in a baremetal program loaded via U-Boot?
https://community.nxp.com/thread/398648

LS1021a CSF format: entry point
https://community.nxp.com/thread/391397

Issue in Booting After Enabling Secure Boot
https://community.nxp.com/thread/385980

Detailed boot process LS1021a SD-card-boot and NOR-boot
https://community.nxp.com/thread/430105

LS1021a full boot sequence
https://community.nxp.com/thread/390833

----
Frame memory mapped for System counter is only following:

D5.3 Counter module control and status register summary

The timer frame for timers of following is not implemented:

D5.5 The CNTBaseN and CNTPL0BaseN frames

ARM® Architecture Reference Manual
ARMv7-A and ARMv7-R edition

Look at RZ/G1E sample. Generic Timer control is memory mapped. It means the Generic Timer which is just Increment Counter is enabled through Memory mapped CNTCR register. But, the Physical Timer which is a decremented counter and uses the Generic Timer pulses remains to be enabled and setting up through the assembly code. So, just the enabling code of Generic timer is added in the timer startup function.

----

Regarding booting of LS1021A, I am not sure how the RCW is formed. But, RCW image is written at the starting of NOR flash (This is not necessarily 0x00000000 address). At address 0x00000000, the PBL (Pre-Boot Loader) is running and this PBL will load the Jump address (from the RCW) to the Scratch Read / Write Register 1 (DCFG_CCSR_SCRATCHRW1) that is Entry address of program in NOR flash. The program in NOR flash needs to initialize the DDR memory.

----

RCW at starting address of NOR flash (0x60000000):

60000000: 55aa55aa 0001ee01 0a000806 00000000    .U.U............
60000010: 00000000 00000000 00000020 00794000    ........ ....@y.
60000020: 005a02e0 00600421 00000000 00000000    ..Z.!.`.........
60000030: 00000000 00800320 00000800 40731b88    .... .........s@
60000040: 00000000 00000000 00025709 ffffffff    .........W......
60000050: 58015709 00030000 7c004089 0073f421    .W.X.....@.|!.s.
60000060: 7c005089 0073f421 0002ee09 0000f867    .P.|!.s.....g...
                                                        ~~~~~~~~~~★ Entry address of program in NOR flash
60000070: 40006108 ad5985f6 ffffffff ffffffff    .a.@..Y.........

The entry address are written to Scratch Read / Write Register 1 by the command sequence.

NAND and NOR flash

Book; Building embedded systems

Multicore

PowerPC timebase synchronization

http://www.tentech.ca/2010/09/easy-multi-core-powerpc-timebase-synchronization-with-simics/

L2 Cache during MultiCore

No L2 Cache at all - Neither CPU0 nor CPU1 enabled/disabled L2 Cache
CPU0 enable L2 Cache - CPU1 should not access at all. Initialization should not do disable/enable L2 access. Application programs not only access L2 cache, but L1 cache too. Because, the data is still cached in L2 cache.

Meaning of ACTLR.smp

https://community.arm.com/thread/3092

How to divide the L2 cache between the cores on a ARM Cortex-A7?

http://stackoverflow.com/questions/30612687/how-to-divide-the-l2-cache-between-the-cores-on-a-arm-cortex-a7

Coresight Debug Insights

https://community.arm.com/groups/processors/blog/2015/07/13/how-to-debug-coresight-basics-part-3

Boot loaders

http://www.linaro.org/blog/core-dump/u-boot-on-arm32-aarch64-and-beyond/

https://github.com/linaro-swg/u-boot/tree/master/board/freescale/ls1043ardb
https://github.com/linaro-swg/u-boot

Controlling Booting in AARCH32 or AArch64.

4.3.76 Reset Management Register

Environment setup and U-Boot compile

http://developer.toradex.com/knowledge-base/build-u-boot-and-linux-kernel-from-source-code

GCC stack analysis

https://mcuoneclipse.com/2015/08/21/gnu-static-stack-usage-analysis/

http://zedboard.org/sites/default/files/blogger_importer/08/zedboard-bring-up.html

https://github.com/zynqgeek/zed_helloworld
http://zedboard.org/content/zedboard-sdk-helloworld-example

For EDK 2016.2

https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-programming-guide/start

Xilinx Wiki

http://www.wiki.xilinx.com/MPSoC+Power+Management

AMP bare metal Vivado
http://www.wiki.xilinx.com/XAPP1079+Latest+Information


GIC - Sup's Wiki
http://ssup2.iptime.org/wiki/ARM_Generic_Interrupt_Controller_(GIC)


MIO - multiplexed I/O (MIO)
EMIO - extended multiplexed I/O interface (EMIO)
EPP - Extensible Processing Platform (EPP)


divide by zero
http://blog.kmckk.com/archives/4170081.html
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0133c/index.html


Artix-7 as PL of Zynq-7020
http://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html

Good linker script

http://hertaville.com/a-sample-linker-script.html


Cortex-A9 Active, but no Pending interrupt
https://community.arm.com/thread/8117
https://community.nxp.com/thread/314843

Source code of GIC interrupts

https://reviews.freebsd.org/file/data/mhsub6nzfe6qhdiwypgb/PHID-FILE-3inesgv5msw2u6deaswa/file

Xilinx API

https://forums.xilinx.com/xlnx/attachments/xlnx/zaps/471/1/api2.pdf


LXR - Marvell 88

http://lxr.free-electrons.com/source/drivers/net/phy/marvell.c#L614
https://lxr.missinglinkelectronics.com/uboot/drivers/net/phy/marvell.c#L283

Zynq FSBL
Software Developers Guide
https://www.xilinx.com/support/documentation/user_guides/ug821-zynq-7000-swdev.pdf

ARMv8 development

https://quequero.org/2014/04/introduction-to-arm-architecture/

ARMv8 difference

zero register - Not r0, but, r31 (WZR - 32 bit, XZR - 64 bit)
stack pointer - Not r13, but r31 (WSP - 32 bit, SP - 64 bit, 16-bytes aligned)
Link register - Not r14, but r30
                     Not banked, but PC is stored in Target Exception level's ELR register
CPSR         - No access as register. But, instructions to atomically modify state bit fields

No direct PC access - Only ADR, ADRP, literal load and direct branches, BL and BLR
                                 Branches, exception generation/return.

No Co-processor. System Instructions
                       System Register access
                        Cache/TLB management
                       VA⇔ＰＡ Translation
                       Barriers and CLREX
                       Architectural hints (WFI, etc)
                       Debug

No multiple LDM, STM, PUSH and POP instructions, but load-store of a non-contiguous pair of registers (LDP, STP).
Extra instructions LDNP, STNP (for atomic update of pair of pointers for example circular list inserts), PRFM (prefetch memory) instructions instruct not to cache data. ex: Streaming and Non-temporal data.

Conditional and predicated execution is not provided, such as IT instruction.
Condition to be appended with "." delimiter to the instruction.

No RRX shift and no ROR shift for ADD/SUB

FPU and NEON extended to 32 128 bit registers (V0 - V31). But, smaller registers no longer packed into larger registers. Just mapped to one-to-one to low order bits of 128-bit registers.
No Soft-Floating pointer. Hardware floating point is must for FP arithmetic.

Most integer instructions two forms to operate either on 32-bit or 64-bit. Assembly notation to distinguish between these two forms.
W - 32 bit word
X - 64 bit extended

// - comment

Same instructions,  but, based on First Operand Register name the operation is different.
ADD            W0, W1, W2   // add 32-bit register
ADD            X0, X1, X2    // add 64-bit register

ADD            X0, X1, W2, SXTW    // add 64-bit extended register
ADD            X0, X1, #42    // add 64-bit immediate

Only the following conditional:
Conditional branch: compare and branch if zero/non-zero, single bit if zero/non-zero.
Add/Subtract with carry.
Conditional select with increment, negate, invert: Conditionally select one source, or another incremented/negated/inverted/unmodified source register.
Conditional Select (move): set the destination to one of two source registers.
Conditional set:  Conditionally select between 0 and 1, or -1.
Conditional compare: Sets condition flags to result of comparison or immediate value

Addressing features

Not 32 bit virtual address. But, 49 bit virtual address (MSB 8 bit of 64-bit pointer is ignored)

ARMv8 development

https://quequero.org/2014/04/introduction-to-arm-architecture/

ARMv8 difference

zero register - Not r0, but, r31
stack pointer - Not r13, but r31
Link register - Not r14, but r30
                     Not banked, but PC is stored in Target Exception level's ELR register
CPSR         - No access as register. But, instructions to atomically modify state bit fields

No direct PC access - Only ADR, ADRP, literal load and direct branches, BL and BLR
                                 Branches, exception generation/return.

No Co-processor. System Instructions
                       System Register access
                        Cache/TLB management
                       VA⇔ＰＡ Translation
                       Barriers and CLREX
                       Architectural hints (WFI, etc)
                       Debug

No multiple LDM, STM, PUSH and POP instructions, but load-store of a non-contiguous pair of registers (LDP, STP).
Extra instructions LDNP, STNP (for atomic update of pair of pointers for example circular list inserts), PRFM (prefetch memory) instructions instruct not to cache data. ex: Streaming and Non-temporal data.

Conditional and predicated execution is not provided, such as IT instruction.
Condition to be appended with "." delimiter to the instruction.

No RRX shift and no ROR shift for ADD/SUB

FPU and NEON extended to 32 128 bit registers. But, smaller registers no longer packed into larger registers. Just mapped to one-to-one to low order bits of 128-bit registers.
No Soft-Floating pointer. Hardware floating point is must for FP arithmetic.

Most integer instructions two forms to operate either on 32-bit or 64-bit. Assembly notation to distinguish between these two forms.
W - 32 bit word
X - 64 bit extended

// - comment

Same instructions,  but, based on Register name the operation is different.
ADD            W0, W1, W2   // add 32-bit register
ADD            X0, X1, X2    // add 64-bit register

ADD            X0, X1, W2, SXTW    // add 64-bit extended register
ADD            X0, X1, #42    // add 64-bit immediate

Only the following conditional:
Conditional branch: compare and branch if zero/non-zero, single bit if zero/non-zero.
Add/Subtract with carry.
Conditional select with increment, negate, invert: Conditionally select one source, or another incremented/negated/inverted/unmodified source register.
Conditional Select (move): set the destination to one of two source registers.
Conditional set:  Conditionally select between 0 and 1, or -1.
Conditional compare: Sets condition flags to result of comparison or immediate value

Addressing features

Not 32 bit virtual address. But, 49 bit virtual address (MSB 8 bit of 64-bit pointer is ignored)

zynq ethernet

https://github.com/littlekernel/lk/blob/master/platform/zynq/gem.c
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/net/ethernet/xilinx/xilinx_emacps.c
http://www.keil.com/dd/docs/arm/atmel/rm9200/at91rm9200.h
https://github.com/Xilinx/linux-xlnx/blob/52830813b4b1183c1dd9d664f54019be83cf335a/arch/arm/include/asm/barrier.h


Boot CPU1 in AMP mode
https://qiita.com/7of9/items/3a68aaa9ef800fa480a2
https://japan.xilinx.com/support/answers/46911.html
https://forums.xilinx.com/t5/Processor-System-Design/Bare-Metal-System-Running-on-Both-Cortex-A9-Processors/td-p/807939
https://stackoverflow.com/questions/43667647/running-xapp1079-on-a-zynq-board

Good blog for Electronic projects

https://dmohankumar.wordpress.com/2012/08/14/8107/

Giga Bit ethernet has full duplex only

http://sqlblog.com/blogs/joe_chang/archive/2010/03/23/gigabit-and-full-duplex.aspx

Giga bit only autonegotiates.

Fast memcpy in c

http://www.danielvik.com/2010/02/fast-memcpy-in-c.html

i.MX6UL ENET source in linux

http://www.oryx-embedded.com/doc/mk60__eth_8c_source.html

To configure my DELL Vostro Ubuntu as WiFi Gateway

#/home/su../nat.sh

echo -e "\n\nLoading simple rc.firewall-iptables version $FWVER..\n"
DEPMOD=/sbin/depmod
MODPROBE=/sbin/modprobe

EXTIF="wlan0"
INTIF="eth0"
#INTIF2="eth0"
echo "   External Interface:  $EXTIF"
echo "   Internal Interface:  $INTIF"

#======================================================================
#== No editing beyond this line is required for initial MASQ testing ==
echo -en "   loading modules: "
echo "  - Verifying that all kernel modules are ok"
$DEPMOD -a
echo "----------------------------------------------------------------------"
echo -en "ip_tables, "
$MODPROBE ip_tables
echo -en "nf_conntrack, "
$MODPROBE nf_conntrack
echo -en "nf_conntrack_ftp, "
$MODPROBE nf_conntrack_ftp
echo -en "nf_conntrack_irc, "
$MODPROBE nf_conntrack_irc
echo -en "iptable_nat, "
$MODPROBE iptable_nat
echo -en "nf_nat_ftp, "
$MODPROBE nf_nat_ftp
echo "----------------------------------------------------------------------"
echo -e "   Done loading modules.\n"
echo "   Enabling forwarding.."
echo "1" > /proc/sys/net/ipv4/ip_forward
echo "   Enabling DynamicAddr.."
echo "1" > /proc/sys/net/ipv4/ip_dynaddr
echo "   Clearing any existing rules and setting default policy.."

iptables-restore <<-EOF
*nat
-A POSTROUTING -o "$EXTIF" -j MASQUERADE
COMMIT
*filter
:INPUT ACCEPT [0:0]
:FORWARD DROP [0:0]
:OUTPUT ACCEPT [0:0]
-A FORWARD -i "$EXTIF" -o "$INTIF" -m conntrack --ctstate ESTABLISHED,RELATED -j ACCEPT
-A FORWARD -i "$INTIF" -o "$EXTIF" -j ACCEPT
-A FORWARD -j LOG
COMMIT
EOF

echo -e "\nrc.firewall-iptables v$FWVER done.\n"

MicroBlaze Version Vs EDK version

http://blog.gpjtag.com/?p=788

Reverse bytes

http://www.openbeacon.org/git-view/openbeacon/plain/firmware/at91sam7/openbeacon-openpicc2/application/nfc/pn532.c?id=v0.0.7
https://github.com/merbanan/rtl_433/pull/162/files

Ethernet flow control

http://rickardnobel.se/esxi-and-flow-control/

ZC-702

Documentation


http://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html#documentation

EWARM STACK placement and linker defined symbols

Are We Shooting Ourselves in the Foot with Stack Overflow?

http://embeddedgurus.com/state-space/2014/02/are-we-shooting-ourselves-in-the-foot-with-stack-overflow/

Vectorization

http://www.doulos.com/knowhow/arm/using_your_c_compiler_to_exploit_neon/Resources/using_your_c_compiler_to_exploit_neon.pdf


Using IAR Embedded Workbench for ARM compiler vectorization ..
https://www.iar.com/support/resources/articles/automatic-neon-vectorization/




https://www.google.co.jp/?gfe_rd=cr&ei=Tv7wVqHIGKzU8Afv0oHADg#q=gcc+howto+use+pragma+to+disable+vectorization
(How to user pragma to disable vectorization)
http://stackoverflow.com/questions/7778174/how-can-i-disable-vectorization-while-using-gcc


C:\Program Files (x86)\KPIT\GNUARM-NONEv15.01-EABI\Doc\optimization_in_GCC.html


For ARM CC


http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472j/chr1359124210006.html


List of options - Keil
http://www.keil.com/support/man/docs/armcc/armcc_chr1359124992544.htm


http://www.slideshare.net/linaroorg/using-gcc-autovectorizer


novector GCC
http://www.isus.jp/article/compileroptimization/compiler_part6/


Branch Prediction - Cortex-A initialization

https://chromium.googlesource.com/native_client/nacl-newlib/+/99fc6c167467b41466ec90e8260e9c49cbe3d13c/libgloss/arm/cpu-init/rdimon-aem.S

ARM ADS

--list

This option instructs the compiler to generate raw listing information for a source file. The name of the raw listing file defaults to the name of the input file with the filename extension .lst.


http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0491c/CHDDIBFD.html




GENMAI sample


http://japan.renesas.com/products/mpumcu/rz/rza/rza1h/Application_Notes.jsp




LDR (PC relative)
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/Babcjaii.html
http://www.sciencezero.org/index.php?title=ARM:_Cortex-M3_Thumb-2_instruction_set


Section placement and Scatter loading in ARM
http://www.keil.com/support/man/docs/armlink/armlink_pge1362065968963.htm


Load$$LR$$ load region symbols
http://www.keil.com/support/man/docs/armlink/armlink_pge1362065953823.htm




Loading linker symbol


http://infocenter.arm.com/help/topic/com.arm.doc.dui0474l/DUI0474L_armlink_user_guide.pdf
32-bit applications
Create a 32-bit data word to hold the value of the symbol, for example:
IMPORT |Image$$ZI$$Limit|
…
zi_limit DCD |Image$$ZI$$Limit|
To load the value into a register, such as r1, use the LDR instruction:
LDR r1, zi_limit
The LDR instruction must be able to reach the 32-bit data word. The accessible memory range varies
between ARM and Thumb, and the architecture you are using.

Mulitcore iTRON: Concept collection

http://www.noble-library.org/papers.html



http://pubman.mpdl.mpg.de/pubman/item/escidoc:1819096:3/component/escidoc:1840714/MPI-I-2007-1-003.p

What is Lock-Free?


Like your Futex implementation, just use Hardware atomic operations to check availability of access and atomically lock the resources. But, when there is failure on checking the availability, still it returns with FALSE. It does not block.



What is Wait-Free?


Hard real time systems requires this. Waiting also limited and guranteed.


Lock-free vs. wait-free concurrency




http://rethinkdb.com/blog/lock-free-vs-wait-free-concurrency/


The lockless page cache patches to the Linux kernel are an example of a wait-free system.
The lockless page cache
http://lwn.net/Articles/291826/
http://www.barrelfish.org/peter-phd-multicore-resource-mgmt.pdf




http://users.ece.utexas.edu/~valvano/EE345M/Arm_EE382N_4.pdf

Read

http://www.embedded.com/design/mcus-processors-and-socs/4007148/Building-Bare-Metal-ARM-Systems-with-GNU-Part-7


Interwork


https://wiki.ubuntu.com/ARM/Thumb2PortingHowto
https://answers.launchpad.net/gcc-arm-embedded/+question/231518


Softfp and Hard ABI


https://bugs.chromium.org/p/v8/issues/detail?id=2140

Undefined Reference

(.text.get_num_and_scan+0x20): undefined reference to `isdigit'


http://renesasrulz.com/renesas_forum_home/rl78/f/26/t/5069.aspx


Clear BSS section in ARM


http://www.keil.com/support/docs/2821.htm

ARM volatile and non-volatile

http://stackoverflow.com/questions/261419/arm-to-c-calling-convention-registers-to-save


To summarize:

• r0-r3 are not callee-saved
• r4-r11 are callee-saved
• r12 (alias ip) is not callee-saved
• r13 (alias sp) is callee-saved
• r14 (alias lr) is not callee-saved
• r15 (alias pc) is the program counter and is set to the value of lr prior to the function call

ARM good assembly reference


http://milkpot.sakura.ne.jp/note/arm.html


Unsigned Comparison ARM
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473j/dom1359731162080.html


Synonyms of PUSH, POP
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489e/Babefbce.html


Calling convention for different CPUs:
http://www.ertl.jp/~takayuki/readings/info/no04.html

SH7753EVB

http://lxr.free-electrons.com/source/drivers/net/phy/vitesse.c
http://www.ieee802.org/3/ab/public/nov97/1gig.an.presentation1.pdf
http://lxr.free-electrons.com/source/drivers/net/ethernet/renesas/sh_eth.c#L970


Clear ITLB before PMB mapping.
http://lists.denx.de/pipermail/u-boot/2013-December/169411.html