ARM MMU

Good link to read and follow up.
https://www.embedded-bits.co.uk/2011/mmucode/

LDMFD sp!, {lr, pc}

https://android.googlesource.com/kernel/lk/+/master/arch/arm/exceptions.S

PCIe development on SABRE boards

https://community.nxp.com/thread/328842

http://www.silexamerica.com/products/connectivity-solutions/embedded-wireless/pcie-radios/sx-pcean2/
Mini PCI → 18 pins one side 8 pins other side

PCI Express × 1 → 11 pin one side 7 pins other side
https://en.wikipedia.org/wiki/PCI_Express

https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/Simple-example-of-ML605-PCIe/td-p/122484


PCIe to Mni PCIe adapter

http://www.bplus.com.tw/Adapter/PM2C.html

http://www.digikey.com/en/product-highlight/v/versalogic/mini-pcie-modules
VL-MPEe-E3E

http://www.digikey.com/en/product-highlight/v/versalogic/mini-pcie-modules


Good Insight to PCI Express
http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1

Simple Chip Serial with PCIe interface (Exar XR17V354)
https://www.exar.com/content/document.ashx?id=1586

http://versalogic.com/support/product_support.asp?ProductID=236


Xilinx DMA endpoint
https://www.xilinx.com/Attachment/Xilinx_Answer_65444_2016_1.pdf

NXP i.MX6 DMA access
https://community.nxp.com/thread/305942


i.MX6Q PCIe EP/RC Validation System
https://community.nxp.com/docs/DOC-95014

Translation

https://books.google.co.in/books?id=Ji43AQAAMAAJ&pg=PR9&lpg=PR9&dq=%22shall+consult%22&source=bl&ots=gbjktyF92m&sig=7wP581prH4uX6ENP1WkarQ4AS7Q&hl=en&sa=X&ved=0ahUKEwj1lcLSubLRAhWKNI8KHeorD98Q6AEIOzAI#v=onepage&q=%22shall%20consult%22&f=false

https://cozy-japan.com/terms.php

http://www.city.ota.gunma.jp/005gyosei/0040-001koukin-tax/files/H27Tax_Payment_Issuance_Application_EN.pdf

Things to be taken when travel

license dongles
Hard disk

--
Keep Latest backup of mails

NTP

NTP Japanese article

http://www.atmarkit.co.jp/ait/articles/1203/15/news121.html

Xilinx AXI Ethernet

http://lxr.free-electrons.com/source/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
http://lxr.free-electrons.com/source/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c#L20


Half-Duplex Mode: When this bit is 1, the transmitter operates in
half-duplex mode. When this bit is 0, the transmitter operates in
full-duplex mode. Only full-duplex is supported so this bit should
always be set to 0.

There is basically difference between Marvell 88E1111S and 88E1011S. But, lanphy.c has 88E1011S settings for 88E1111S. Refer to the following:
https://github.com/Xilinx/u-boot-xlnx/blob/master/drivers/net/phy/marvell.c

88E1111S  Vs 88E1116R
http://svn.dd-wrt.com/browser/src/linux/universal/linux-3.12/drivers/net/phy/marvell.c?rev=22733

Microblaze version tracking

#define __GNUC__ 5

#define __GNUC_MINOR__ 2

#define __GNUC_PATCHLEVEL__ 0

For example,

http://lxr.free-electrons.com/source/include/linux/compiler.h?v=2.4.37

http://www.boost.org/doc/libs/1_61_0/boost/optional/detail/optional_config.hpp

GCC assembler comments style differs based on architecture. For PowerPC and MicroBlaze, it is #. For ARM, it is @.


SDK version GCC version
SDK 2019.1          8.2
SDK 2018.3          7.3
SDK 2018.2          7.2
SDK 2018.1          7.2
SDK 2017.4 6.2
SDK 2017.3 6.2
SDK 2016.4 5.2
SDK 2016.3 5.2
SDK 2016.1 5.2 (Upgraded to)
SDK 2015.4 4.9.2
SDK 2015.3 4.9.2
SDK 2015.1 4.9.2 (Upgraded to)
SDK 2014.1 4.8.3 (Upgraded to)
SDK 14.5/2013.1
EDK14.1 4.6.2


https://www.xilinx.com/support/answers/55776.html


GCC version comparison

https://sourceforge.net/p/stxxl/git/ci/61b7fe42d2ff7ae5157049b720793c380450c6c2/tree/include/stxxl/bits/compat/shared_ptr.h?barediff=e95b9e0556953f21f002d9128de5becbba68b98e

https://gcc.gnu.org/onlinedocs/gcc-4.0.2/cpp/Common-Predefined-Macros.html


Fast Simplex Link (FSL) Interface Description
The Fast Simplex Link bus provides a point-to-point communication channel between an output FIFO and an input FIFO.

Interrupt Level Control By Software


http://google.co.kr/patents/US20050193260