The perfect devices

Thursday, March 3, 2016

This option instructs the compiler to generate raw listing information for a source file. The name of the raw listing file defaults to the name of the input file with the filename extension .lst.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0491c/CHDDIBFD.html

GENMAI sample

http://japan.renesas.com/products/mpumcu/rz/rza/rza1h/Application_Notes.jsp

LDR (PC relative)
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/Babcjaii.html
http://www.sciencezero.org/index.php?title=ARM:_Cortex-M3_Thumb-2_instruction_set

Section placement and Scatter loading in ARM
http://www.keil.com/support/man/docs/armlink/armlink_pge1362065968963.htm

Load$$LR$$ load region symbols
http://www.keil.com/support/man/docs/armlink/armlink_pge1362065953823.htm

Loading linker symbol

http://infocenter.arm.com/help/topic/com.arm.doc.dui0474l/DUI0474L_armlink_user_guide.pdf
32-bit applications
Create a 32-bit data word to hold the value of the symbol, for example:
IMPORT |Image$$ZI$$Limit|
…
zi_limit DCD |Image$$ZI$$Limit|
To load the value into a register, such as r1, use the LDR instruction:
LDR r1, zi_limit
The LDR instruction must be able to reach the 32-bit data word. The accessible memory range varies
between ARM and Thumb, and the architecture you are using.

http://www.noble-library.org/papers.html

http://pubman.mpdl.mpg.de/pubman/item/escidoc:1819096:3/component/escidoc:1840714/MPI-I-2007-1-003.p

What is Lock-Free?

Like your Futex implementation, just use Hardware atomic operations to check availability of access and atomically lock the resources. But, when there is failure on checking the availability, still it returns with FALSE. It does not block.

What is Wait-Free?

Hard real time systems requires this. Waiting also limited and guranteed.

Lock-free vs. wait-free concurrency

http://rethinkdb.com/blog/lock-free-vs-wait-free-concurrency/

The lockless page cache patches to the Linux kernel are an example of a wait-free system.
The lockless page cache
http://lwn.net/Articles/291826/
http://www.barrelfish.org/peter-phd-multicore-resource-mgmt.pdf

http://users.ece.utexas.edu/~valvano/EE345M/Arm_EE382N_4.pdf

(.text.get_num_and_scan+0x20): undefined reference to `isdigit'

http://renesasrulz.com/renesas_forum_home/rl78/f/26/t/5069.aspx

Clear BSS section in ARM

http://www.keil.com/support/docs/2821.htm

r0-r3 are not callee-saved
r4-r11 are callee-saved
r12 (alias ip) is not callee-saved
r13 (alias sp) is callee-saved
r14 (alias lr) is not callee-saved
r15 (alias pc) is the program counter and is set to the value of lr prior to the function call

ISR:

push {lr}
bl ent_int
bl isr
pop {lr}
b ret_int

ent_int:

tcb->sp should point to the t_ctx structure so that inside interrupt handler the system calls can refer tcb->sp->wid and tcb->sp->ercd etc.

https://github.com/DISTORTEC/distortos/blob/master/source/architecture/ARM/ARMv7-M/ARMv7-M-PendSV_Handler.cpp

http://stackoverflow.com/questions/25199802/switching-context-inside-an-isr-on-cortex-m