NIOS Porting steps

BSP Creation

1) Nios V/g Use Intel® Arria® 10 FPGA - Hello World on the Nios® V/g Processor Design Example

(a0 and t2 registers could not be written or read correctly in Nios V/m)

1) Patch files created with reference to

C:\intelFPGA_pro\23.2\ip\altera\soft_processor\altera_hal2\HAL

and updated the same with script file using the $QUARTUS_ROOTDIR.

Administrator rights is necessary.

2) sample BSP creation testing..

with reference to \top_project\readme.txt, in NIOS V command shell, the following commands are executed. Some projects need "quartus_py scripts/build_sof.py" command to avoid NIOS V cpu is not specified in the hardware project.

i) niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/sys.qsys --type=hal sw/bsp_smp/settings.bsp

ii) niosv-app --bsp-dir=sw/bsp_smp --app-dir=sw/app_smp --srcs=sw/app_smp/hello.c

iii) niosv-shell

iv) cmake -S ./sw/app_smp -G "Unix Makefiles" -B sw/app_smp/build

v) make -C sw/app_smp/build

vi) Program the FPGA using programmer

vii) using separate shell, "juart-terminal -c 1 -i 0"

viii) niosv-download -g sw/app_smp/build/app_smp.elf -c 1

BSP Build using the MACRO defined

add_definitions(-DXXXXx)

TCL programming: Check the NIOS V Processor Developer Handbook itself.