Friday, May 31, 2019

ML7304 supports only Little Endian

http://www.lapis-semi.com/jp/data/user's%20manual-file_db/telecom/FJUL7304-0X2IPFULL-F83-1.0.pdf

【注意】 CPU のアーキテクチャではビッグエンディアンあるいはリトルエンディアンのいずれかを選択してメモリ中のワードを扱 うことができますが、本 LSI ではリトルエンディアンに固定されています。

Wednesday, May 29, 2019

Tuesday, May 28, 2019

Echo Tool

2. From the command window, type echotool 192.168.0.102 /p tcp /r 7 /d hello
NOTE: The echotool.exe application can be found here https://github.com/PavelBansky/EchoTool

Monday, May 27, 2019

To edit photos online

https://www110.lunapic.com/editor/

Draw -> Paint bucket tool -> Select the image in clipboard -> Select clipboard in Pattern -> click the color to be filled in.

Tuesday, May 21, 2019

GNU GCC linker - Ordering a particular object file

MEMORY {
    SDRAM_1   (rwx) : ORIGIN = 0x4c000000, LENGTH = 0x00100000
    SDRAM_2   (rw)  : ORIGIN = 0x4c100000  LENGTH = 0x00200000
    SPIFLASH  (rw)  : ORIGIN = 0x30000000  LENGTH = 0x000FFFFF
}

ENTRY(__RESET)
EXTERN(SPIBOOT)

SECTIONS {

    .rom : {
        . = 0x00000000;
        * (.boot_param)
        PROVIDE(__rom_code = .);
    } > SPIFLASH

    .text : AT ( __rom_code ) {
        PROVIDE(__ro_start__ = .);
        . = 0x00000000;
          * (.vectors)

        . = 0x00000200;
          * (INIT)
          *aprzt0a.o (.text .text.*)
          * (.text .text.*)
          * (.rodata .rodata.*)
        PROVIDE(__ro_end__ = .);
    } > SDRAM_1

Sunday, May 19, 2019

EWARM Link guide

https://www.iar.com/globalassets/2/ew_ilinkguide.jpn_20131006.pdf

If you refer SFE(.text) or SFB(.text), the linker does not obey to your rules in your linker definition file and it just clubs all together to find the end and start of .text section. Use block instead as follows:

define block TEXT with fixed order { rw code object mpu7r.o, rw code object rskrat1.o, rw code };
define block TEXT_init with fixed order { ro code object mpu7r.o, ro code object rskrat1.o, ro code };

----
Even Text and .rodata can be split as follows:
define block TEXT { ro code };
define block RODATA { readonly };

Saturday, May 11, 2019

MicroChip PHYs

 * Giga phys: ksz9021, ksz9031, ksz9131

 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
 *    ksz8021, ksz8031, ksz8051,
 *    ksz8081, ksz8091,
 *    ksz8061,

 * Switch : ksz8873, ksz886x
 * ksz9477s

I had said that Marvell 88E1152 was similar to 88E111x and EEE erratta needs to be added. But, it was wrong. The registers for RGMII Delay and RGMII Copper mode settings were completely different and the default setup supports both on 88E1152. I removed any 88E1152 specific setting.


RZ/N1D Ethernets

Tuesday, May 7, 2019

RZ/N1 Further clarity

RZ/N1D/S/L has Double/Single/Zero cores of Cortex-A7.
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzn/rzn1.html
So, better to have separate start-ups for each.

Please refer to “CoreLink™ GIC-400 Generic Interrupt Controller Technical Reference Manual” on Arm website.

Clocks got as follows:

Timer clock is got from CNTFRQ register as follows:
        mrc     p15, #0, r0, c14, c0, #0

How is it derived is not known yet. Other serial and Ethernet are as follows: