Arria V SoC
For DS-5 connection:
Check "Preparing the Board for the Board Test System" of following:
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_av_soc_dev_kit.pdf
Power Connection is LTE60E-S3-3.
For Jumper settings, for USB Blaster II, short both JTAG SEL (J21) and JTAG HPS SEL (J19).
Helio Cyclone V SoC
When bringing the board, SW1-1, SW1-2 were in Off position. I made them ON for using USB Blaster. SW4-2 was in ON position. I made it to Off position.
https://service.macnica.co.jp/article_files/118693/ELS1422_Q1500_10__1.pdf
https://www.altima.jp/members/p1-literature/1-software/1-altera/2016008_soc_bgnr_baremetal.cfm
Xillibus
http://xillybus.com/tutorials/u-boot-image-altera-soc
For DS-5 connection:
Check "Preparing the Board for the Board Test System" of following:
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_av_soc_dev_kit.pdf
Power Connection is LTE60E-S3-3.
For Jumper settings, for USB Blaster II, short both JTAG SEL (J21) and JTAG HPS SEL (J19).
Helio Cyclone V SoC
When bringing the board, SW1-1, SW1-2 were in Off position. I made them ON for using USB Blaster. SW4-2 was in ON position. I made it to Off position.
https://service.macnica.co.jp/article_files/118693/ELS1422_Q1500_10__1.pdf
https://www.altima.jp/members/p1-literature/1-software/1-altera/2016008_soc_bgnr_baremetal.cfm
Xillibus
http://xillybus.com/tutorials/u-boot-image-altera-soc
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