Cyclone V SoCs
https://www.altera.com/products/soc/portfolio/cyclone-v-soc/support.html
Booting CPU1
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-v/cv_5400a.pdf#page=4
1) After Booting CPU0, Map Boot ROM to Reset vector.
2) Assign CPU1 start address to register cpu1startaddr (0xFFD080C4)
3) Release CPU1 from reset
*cpu1startaddr register is in boot ROM code register group (romcodegrp) in the system manager.
--
Boot ROM
Boot Region (Page 458 of Technical Reference Manual)
The boot region is 1 MB, based at address 0x0. The boot region is visible to the MPU only when the L2 address filter start register is set to 0x100000. The L3 remap control register determines if the boot region is mapped to the on-chip RAM or the boot ROM.
The boot region is mapped to the boot ROM on reset. Only the lowest 64 KB of the boot region are legal addresses because the on-chip RAM and boot ROM are only 64 KB.
When the L2 address filter start register is set to 0, SDRAM obscures access to the boot region. This technique can be used to gain access to the lowest SDRAM addresses after booting completes.
----
0x00000000 ～ 0x00100000 address is compete whether to map SDRAM or BootROM Region. BootROM region itself is compete whether mapping On-Chip RAM or Boot ROM.
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remap Register (0xFF800000)
mpuzero
Controls whether address 0x0 for the MPU L3 master is mapped to the Boot ROM or On-chip RAM. This field only has an effect on the MPU L3 master.
0x0
Maps the Boot ROM to address 0x0 for the MPU L3 master. Note that the Boot ROM is also always mapped to address 0xfffd0000 for the MPU L3 master independent of this field's value.
0x1
Maps the On-chip RAM to address 0x0 for the MPU L3 master. Note that the On-chip RAM is also always mapped to address 0xffff_0000 for the MPU L3 master independent of this field's value.
Release Reset
After CPU0 comes out of reset, it can deassert CPU1's reset signals by clearing the CPU1 bit in the MPU Module Reset (mpumodrst) register in the Reset Manager.
Address Filtering (Page 709)
This address space is allocated for address filtering registers.
0xFFFEFC00
CPU1 Boot Linux
http://lugman.org/images/d/d3/161022-Caricamento_Baremetal_x_AMP.pdf
HELIO Resources
https://rocketboards.org/foswiki/Documentation/HelioResourcesForRev14
https://www.altera.com/products/soc/portfolio/cyclone-v-soc/support.html
Booting CPU1
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-v/cv_5400a.pdf#page=4
1) After Booting CPU0, Map Boot ROM to Reset vector.
2) Assign CPU1 start address to register cpu1startaddr (0xFFD080C4)
3) Release CPU1 from reset
*cpu1startaddr register is in boot ROM code register group (romcodegrp) in the system manager.
--
The user software in CPU0 is responsible to release CPU1 from reset. If CPU1 is released from reset with
the boot ROM mapped to the reset exception address, the boot ROM code jumps to the value in the CPU1
start address (cpu1startaddr) in the boot ROM code register group (romcodegrp) in the system manager.
--
Boot ROM
Boot Region (Page 458 of Technical Reference Manual)
The boot region is 1 MB, based at address 0x0. The boot region is visible to the MPU only when the L2 address filter start register is set to 0x100000. The L3 remap control register determines if the boot region is mapped to the on-chip RAM or the boot ROM.
The boot region is mapped to the boot ROM on reset. Only the lowest 64 KB of the boot region are legal addresses because the on-chip RAM and boot ROM are only 64 KB.
When the L2 address filter start register is set to 0, SDRAM obscures access to the boot region. This technique can be used to gain access to the lowest SDRAM addresses after booting completes.
----
0x00000000 ～ 0x00100000 address is compete whether to map SDRAM or BootROM Region. BootROM region itself is compete whether mapping On-Chip RAM or Boot ROM.
----
remap Register (0xFF800000)
mpuzero
Controls whether address 0x0 for the MPU L3 master is mapped to the Boot ROM or On-chip RAM. This field only has an effect on the MPU L3 master.
0x0
Maps the Boot ROM to address 0x0 for the MPU L3 master. Note that the Boot ROM is also always mapped to address 0xfffd0000 for the MPU L3 master independent of this field's value.
0x1
Maps the On-chip RAM to address 0x0 for the MPU L3 master. Note that the On-chip RAM is also always mapped to address 0xffff_0000 for the MPU L3 master independent of this field's value.
Release Reset
After CPU0 comes out of reset, it can deassert CPU1's reset signals by clearing the CPU1 bit in the MPU Module Reset (mpumodrst) register in the Reset Manager.
Address Filtering (Page 709)
This address space is allocated for address filtering registers.
0xFFFEFC00
CPU1 Boot Linux
http://lugman.org/images/d/d3/161022-Caricamento_Baremetal_x_AMP.pdf
HELIO Resources
https://rocketboards.org/foswiki/Documentation/HelioResourcesForRev14
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