EVMK2G

Software:

http://www.tij.co.jp/tool/jp/processor-sdk-k2g

Wiki:
http://processors.wiki.ti.com/index.php/66AK2G02_GP_EVM_Hardware_Setup

ARM Cortex-A15
http://processors.wiki.ti.com/index.php/Processor_SDK_Bare_Metal_Examples

About using TI compiler for Cortex-A15

https://e2e.ti.com/support/development_tools/compiler/f/343/t/382886

https://e2e.ti.com/support/development_tools/compiler/f/343/t/599102

Timer interrupt occurs only in non-secure mode

The CPU may be in insecure mode. Please look at SCR.NS bit.

MRC p15, 0, <Rt>, c1, c1, 0; Read Secure Configuration Register data
MCR p15, 0, <Rt>, c1, c1, 0; Write Secure Configuration Register data

The initialization script file had changed the CPU to non-secure mode. Also, the GIC had been configured (IGROUP registers) to interrupt only in non-secure mode.

66AK2G UART0 Interrupt does not occur in ARM core

UART0 interrupt needs to be configured as edge.

Ethernet subsystem
https://lxr.missinglinkelectronics.com/uboot/arch/arm/mach-keystone/include/mach/hardware-k2g.h#L69

https://lxr.missinglinkelectronics.com/linux/drivers/net/ethernet/ti/netcp_ethss.c

http://processors.wiki.ti.com/index.php/Linux_Core_NetCP_User%27s_Guide

U-Boot
https://lxr.missinglinkelectronics.com/uboot/drivers/dma/keystone_nav.c#L50
https://lxr.missinglinkelectronics.com/uboot/drivers/net/keystone_net.c#L503
https://lxr.missinglinkelectronics.com/uboot/include/configs/k2g_evm.h#L84
https://github.com/RobertCNelson/u-boot/blob/master/board/ti/ks2_evm/mux-k2g.h
https://lxr.missinglinkelectronics.com/uboot/board/ti/ks2_evm/board_k2g.c

KeyStone Architecture Multicore Navigator
http://www.ti.com/lit/ug/sprugr9h/sprugr9h.pdf
http://processors.wiki.ti.com/images/f/f0/Eindhoven_JAN_12-06_MulticoreNavigator.pdf

Multicast
http://processors.wiki.ti.com/index.php/Linux_Core_CPSW_User's_Guide

Cache Invalidate Issue:
http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/sysbios/6_42_03_35/exports/bios_6_42_03_35/docs/cdoc/ti/sysbios/family/arm/a15/Cache.html
https://elixir.free-electrons.com/linux/latest/source/arch/arm/mm/proc-v7.S
https://e2e.ti.com/support/embedded/tirtos/f/355/t/544363

reload fails when cache is enabled Cortex-a15
https://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/619005

https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/341333
http://processors.wiki.ti.com/index.php/Debugging_Cortex_A15
https://lists.denx.de/pipermail/u-boot/2012-November/139029.html

U-Boot standalone application - Cache consideration
https://www.denx.de/wiki/view/DULG/UBootStandalone

NEON Test
http://processors.wiki.ti.com/index.php/Cortex-A8#How_to_enable_NEON
-o3 -mv7a8 --neon -mf (--opt_for_speed=5) "

Fused Multiply-Add extension(VFPv4)
http://www.keil.com/support/man/docs/armclang_asm/armclang_asm_pge1427897626943.htm
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473f/CIHJEBCE.html
        fmadd   d1, d2, d3, d4          ; Double-precision

Generic Timer
https://github.com/freebsd/freebsd/blob/master/sys/arm/arm/generic_timer.c

Cygwin Mount on Windows 7

With latest cygwin setup ver 2.882, NFS is as follows,

http://www.morethantechnical.com/2014/01/08/share-nfs-from-windows/

except the following step is not needed, as it gives the ESTALE error if the file system which is going to be mounted is already a mounted one.

----
"5. Due to a strange behavior of Cygwin, you must remount your desired drive as a different mount 

mkdir -p /mnt/d

mount d:/ /mnt/d/

----
Instead I just created a directory as follows,

mkdir -p /mnt/testu

and assigned the owner which automatically had the user and group of "tarner (windows user name)" and "None" respectively. It has "drwxr_xr_x+".
And, added it to /etc/exports as
/mnt/testu (rw,all_squash,anonuid=1000,anongid=513)

And, the following also was not there. It displayed some error. But, it does not matter.

    cygrunsrv --start portmap

The Linux command was,

mount -v -t nfs -o vers=2 192.168.0.35:/mnt/testu share

If Linux, please try any command with -v option to debug easily which is verbose.

Why do we need a capacitor?

https://www.khanacademy.org/questions/why-do-we-need-a/kafb_5416137

Capacitor is used as Dam which will convert the disasters to boon by buffering the wild and irregular flow of water in streams. When surplus flow, it will absorb and when needed it can supply as much as its capacity.

Back pain

http://www.livestrong.com/article/178060-causes-of-lower-abdominal-testicular-pain/

http://fitness4backpain.com/category/diagnosing-your-back-pain/

https://www.lybrate.com/question/744715182/pain-right-leg-pain-starts-back-buttock-front-side-pained-right-testes-little-banocide-forte-tablet-acceclowoc-pain-less-started-pain-leg-buttock-part-knee-foot-times-unable-pain-pain-started-kick-start-bike-everyday-home-hard-pain-due-intestines-due-leg-remedy-worried-alot-previously-right-hand-pain

Arria 10 resources

https://rocketboards.org/foswiki/Projects/A10AVCV171PCIeRootPortWithMSI
file:///C:/Program%20Files/DS-5%20v5.27.1/examples/docs/Altera-Arria-10_RAM/readme.html

http://xillybus.com/tutorials/u-boot-image-altera-soc

Rocketboards
https://rocketboards.org/foswiki/Documentation/WebHome
https://rocketboards.org/foswiki/Documentation/Gsrd131GitTrees#U_45Boot

https://www.altera.com/documentation/suc1427117768942.html

Running both cores in Xilinx SDK

First run cpu0 and then cpu1. otherwise, the interrupt settings by CPU1 will be erased and initiailized by CPU0. So, the LEDs won't glow.

ARM OP Codes

http://denemo.org/~jjbenham/iphone-dev-read-only/odcctools/as/armop.c

https://static.docs.arm.com/dui0742/g/DUI0742G_migration_and_compatibility_guide.pdf

Alignment of functions

https://www.cse.unr.edu/~sushil/class/cs202/help/man/gcc-2.7.0/gcc_82.html
It is not possible to specify the alignment of functions; the alignment of functions is determined by the machine's requirements and cannot be changed.