Wednesday, February 26, 2020
Friday, February 21, 2020
Problems and Solutions
i.MX 6Solox SabreSD platform:
As per U-boot, IOMUX is configured, PHY is configured with Tx/Rx delay and Eth also is as per old driver. But, Transmit was Ok. Receive is just happening two times with 0x40 packet and 0x5F0 packet. The 0x5F0 varies based on the RXBUFLEN value configured in the RX buffer Size Register value.
Solution was the Rx Buffer Size register needs to be configured as 0x600. I do not know what is the reason behind it. But, when U-boot is just stopped in the middle of DHCP command to see the Ethernet values using i-jet debugger (Attach to Running Target).
DMA completes transfer of Data, but packet is not coming out
In i.MX 6SoloX, the MUX Input was not enabled for the Reference clock. Once enabled, it started receiving. After enable Tx delay in PHY, transmission also was Ok.
ENET1 was working, but ENET2 was not working in vein
Everything (all MUX looking at Linux dts file), I did as same as ENET1 except the following:
sfr_outl(ENET2_RX_CLK_INPUT, 1); /* DAISY=1 (pad ENET_MDIO for ENET_MDIO) */
Once I did, it started working.
RT1060 Sample proting: Cortex-M7, when just running the scheduler, execution just to unknown:
Stack No issue, Cache is disabled... But, needed to disable 3 Watchdog Timers.
UART Wrong clock
All clocks except the 480clk needed for UART was missing. (Reverse engineering 80MHz*6)
i.MX RT1060: When Data is placed in OCRAM and Cache Enabled, Exception
As per U-boot, IOMUX is configured, PHY is configured with Tx/Rx delay and Eth also is as per old driver. But, Transmit was Ok. Receive is just happening two times with 0x40 packet and 0x5F0 packet. The 0x5F0 varies based on the RXBUFLEN value configured in the RX buffer Size Register value.
Solution was the Rx Buffer Size register needs to be configured as 0x600. I do not know what is the reason behind it. But, when U-boot is just stopped in the middle of DHCP command to see the Ethernet values using i-jet debugger (Attach to Running Target).
DMA completes transfer of Data, but packet is not coming out
In i.MX 6SoloX, the MUX Input was not enabled for the Reference clock. Once enabled, it started receiving. After enable Tx delay in PHY, transmission also was Ok.
ENET1 was working, but ENET2 was not working in vein
Everything (all MUX looking at Linux dts file), I did as same as ENET1 except the following:
sfr_outl(ENET2_RX_CLK_INPUT, 1); /* DAISY=1 (pad ENET_MDIO for ENET_MDIO) */
Once I did, it started working.
RT1060 Sample proting: Cortex-M7, when just running the scheduler, execution just to unknown:
Stack No issue, Cache is disabled... But, needed to disable 3 Watchdog Timers.
UART Wrong clock
All clocks except the 480clk needed for UART was missing. (Reverse engineering 80MHz*6)
i.MX RT1060: When Data is placed in OCRAM and Cache Enabled, Exception
When Data is placed in OCRAM, Vector table is copied to OCRAM in intini() once after Cache is enabled. And, later the drivers updates the Vector table with its own ISR handler addresses. The both Vector table including the SVC handler addresses and other interrupt handler addresses are just cached and seems not to be updated in physical OCRAM. So, whenever some interrupt occurs or SVC instruction is executed in sysini(), the exception is thrown. (Look at the point where exception is thrown, mainly SVC or other interrupts. It will give clue for fast debugging)
But, since SDRAM is Write-through by default, this problem does not occur when data is placed and the vector table is copied there.
Also, when the exception is traced and the saved LR itself 0xfffffffd, that means exception is thrown on SVC not getting proper handler address.
Prefetch Abort, once MMU is enabled
Old TLB might be used. Make sure that TLB is invalidated before enabling the MMU.
Exception occurs after cache is invalidated
Invalidating entire cache when it is enabled is like you tear your passport while you are using it in abroad. Your stack and other data using currently and recorded in cache itself will be invalidated and you can not even return from where you are.
So, when cache is enabled, use clean and invalidate instruction instead of just invalidate. Similarly, do not clean and invalidate when cache is disabled. Wrong data might overwrite your valid data. Just invalidate when cache is not enabled in your program.
But, since SDRAM is Write-through by default, this problem does not occur when data is placed and the vector table is copied there.
Also, when the exception is traced and the saved LR itself 0xfffffffd, that means exception is thrown on SVC not getting proper handler address.
Prefetch Abort, once MMU is enabled
Old TLB might be used. Make sure that TLB is invalidated before enabling the MMU.
Exception occurs after cache is invalidated
Invalidating entire cache when it is enabled is like you tear your passport while you are using it in abroad. Your stack and other data using currently and recorded in cache itself will be invalidated and you can not even return from where you are.
So, when cache is enabled, use clean and invalidate instruction instead of just invalidate. Similarly, do not clean and invalidate when cache is disabled. Wrong data might overwrite your valid data. Just invalidate when cache is not enabled in your program.
Exception While Running. Does not arise when single stepping
ent_int/ret_int() was missing in LPC54608. Usually, these are default cases for NORTi when exception was caused.
- Stack Overflow: Increase task stack size and interrupt stack size
- Interrupt Handler: Assembly code is not as per NORTi expectation. Optimization level may be causing this. Or, user has dumped all the code in the interrupt handler, not as per NORTi's 3 statement interrupt handler. Or, ent_int/ret_int() has not been added in the interrupt handler.
Execution Jumps to blank location (all zeros memory region, etc)
Execution jumps to blank location and even the Link Register is Zero or invalid address. So, no clue or not able to trace exactly what happened.
It may be the cause of LR register content is corrupted or not restored properly. So, when some function returns with "bx lr", the execution jumps to invalid location. Also, the LR register stays with the same invalid branch address. Here, the debug tip is, to Keep breakpoint in the address which LR register holds. Suppose, if LR is 0, then keep breakpoint at 0th address. The execution jumps to that address from a valid function call. So, you can find the function from where the corruption happened.
Ethernet Connector Does not Lit On
At board Power-On-Reset, the Ethernet Connectors should glow on even before program start-up just by connecting the cable with Hubs. If it does not, that meant the PHY is held in Reset by GPIO pins. Find the GPIO pin that is connected to the PHY Reset, configure it as GPIO in your program and make it Low or High with GPIO data register.
iTRON does not return from dly_tsk()
When testing with highest optimization level -O3 and with NEON enabled kernel library, the TCP test sample program does not return from dly_tsk() called in PHY driver. But, the other sample program works fine.
It is because, with high optimization level and NEON enabled, the stack consumption is very high. So, just increasing the stack size of Tasks is not enough. But, the stack size of idle task (timer handlers) too and interrupt handlers too. In the other sample, these sizes were defined with large size by default. So, that was running. With TCP test case, they were not defined and in idle task the global variable SDISP was not at all reset, since the address that were stored in stack was wrongly referenced because of stack corruption. Because of that, the task was not dispatched even though it is in ready queue.
Ping is inconsistent. Losing response packets
Ping command from host gets some responses, but loses other response packets. Mostly, the PHY configuration is insufficient. Check the Board patch for any specific settings. Clock or Delay settings or LED settings. In RZ/N1D switch, normal GMAC was working fine. But, with the switch, ping was missing packets. The PHY LED[0] needs to be configured for Link.
Debugging MUX, Clock or Other settings
1) Find U-Boot patch. Just go through all the code once to learn about board specific settings.
2) Just copy the register settings when U-Boot was working, make a array[] of values and just overwrite the settings in RTOS.
Saturday, February 15, 2020
Autosys
1) RSLogic - PLC programming
2) Factory Talk View - SCADA
3) CCW (Connected Components Workbench) - HMI
4) How can store data in PLC itself, so that customer can take the data to his PC when needed.
5) Reporting - Storing data in SQL (Database) (With/Without using SCADA)
6) Concentrate on Reporting, Error Display, SCADA operations to display and Animation.
7) Proper documentation software for Software Flow chart to document the Software Process in PLC
--
GA - Requirement Final
Drive List
IO List
Allen Bradley's PLC Programming Handbook
http://www.plcdev.com/book/export/html/431
Informative Videos on Allen Bradley
https://solisplc.com/plc-programming-fundamentals-osr-instruction/
Each Shareholder PLC controller (Memory), HMI, SCADA, Dataserver (OPC) is a Server like QNX. Each share connections (Tags) to be accessed by each other.
Every Component has multiple objects. Each object has a connection (Tag) to read or write values.
Similarly, hardware interfaces too have PLC interfaces to include into program.
Remember almost all components can be exported and imported between multiple projects. So, can use copy and paste like EWARM projects.
The Ladder Logic program should be more readable with enough comments, descriptions, symbols like a good C program. You can write a good C program first, then convert into the Ladder Logic Program.
Read One Model Thoroughly. You will understand what needs to be done for others. Similarly, for your first work, keep the Marks(Goal Height) very high. Because, it will continue for rest of the life.
Use Example Projects Effectively.
For Any Module Hardware component, Get the Manual and Read it. That is it!
What is Remote I/O?
What is SLC and PLC?
Why properties are so important? How are they attached just to a variable?
Just adding extra information at the Server for the variable found in the PLC device, so that they can be shared to the outside world in a more descriptive way. Another way to do it is in HMI where values from devices can be connected to Graphic objects and addition properties such as Limits can be added.
2) Factory Talk View - SCADA
3) CCW (Connected Components Workbench) - HMI
4) How can store data in PLC itself, so that customer can take the data to his PC when needed.
5) Reporting - Storing data in SQL (Database) (With/Without using SCADA)
6) Concentrate on Reporting, Error Display, SCADA operations to display and Animation.
7) Proper documentation software for Software Flow chart to document the Software Process in PLC
--
GA - Requirement Final
Drive List
IO List
Allen Bradley's PLC Programming Handbook
http://www.plcdev.com/book/export/html/431
Informative Videos on Allen Bradley
https://solisplc.com/plc-programming-fundamentals-osr-instruction/
Each Shareholder PLC controller (Memory), HMI, SCADA, Dataserver (OPC) is a Server like QNX. Each share connections (Tags) to be accessed by each other.
Every Component has multiple objects. Each object has a connection (Tag) to read or write values.
Similarly, hardware interfaces too have PLC interfaces to include into program.
Remember almost all components can be exported and imported between multiple projects. So, can use copy and paste like EWARM projects.
The Ladder Logic program should be more readable with enough comments, descriptions, symbols like a good C program. You can write a good C program first, then convert into the Ladder Logic Program.
Read One Model Thoroughly. You will understand what needs to be done for others. Similarly, for your first work, keep the Marks(Goal Height) very high. Because, it will continue for rest of the life.
Use Example Projects Effectively.
For Any Module Hardware component, Get the Manual and Read it. That is it!
What is Remote I/O?
What is SLC and PLC?
Why properties are so important? How are they attached just to a variable?
Just adding extra information at the Server for the variable found in the PLC device, so that they can be shared to the outside world in a more descriptive way. Another way to do it is in HMI where values from devices can be connected to Graphic objects and addition properties such as Limits can be added.
Thursday, February 13, 2020
Autosar: Code generation
Reading and writing configuration for Java application using Properties class
https://www.codejava.net/coding/reading-and-writing-configuration-for-java-application-using-properties-classLook at Gendata\Rte.html for summary.
C code and header files are generated using the configuration under the following XML files:
BswM_XMI21.xml
Com_XMI21.xml
ComM_XMI21.xml
PduR_XMI21.xml
See Rte.c has all header files included where each header file is auto-generated for each Task function. And, inside Rte.c all Task functions are auto-generated. It needs to be trimmed. Gendata folder has all generated files.
----
Main Two files are Auto-generated: tcb.c and rte.c. You need to trim both if you want to minimize the system.
For every task, the XXX_TASK function is auto-generated in Rte.c inside which XXXX_main() is called.
EcuM_StartupTwo()
-----------------------
TaskInterruptFunc() was thought that main interrupt handling function. But, came to know that it is calling IPC module. So, commented out that.
In Develop/PF/PF_SWC_APL/SRC is having source file for all Application modules. Also, it has fc_swc_XXXXX. What is SWC? This source is having some init functions and seems to be important. And, it has IOCTL calls too.
The fc_sys_SysInit() is the Main System initialization function called in SysSyTsk.c of Develop\PF\PF_SYS_MNG\Src.
It is called from fc_swc_TskSysSystem_Init() from SwcTskSysSystem.c of Develop\PF\PF_SWC_APL\Src. And, it has some main interface functions
fc_swc_TskSysSystem_main -
fc_swc_TskSysSystem_system_timer -
fc_swc_TskSysSystem_SendMessage -
fc_swc_TskSysSystem_RecvMessage -
fc_swc_TskSysSystem_SendStatusChange -
From TASK(TskSysSystem), TskSysSystem_Init() is called and from TskSysSystem_Init(), fc_swc_TskSysSystem_Init() is called.
FT_IPAS\includes\most\GmmostGeneral.h has all FBlockID related to ICCOM.
SysSyTsk.c seems to have Platform dependent functions. Needs to be trimmed out.
Monday, February 3, 2020
Saturday, February 1, 2020
Reverse Message
Dxxxx\PDK\xxxx120012\kscv-vehiclefunction\gmlan\src\gmlansource.cpp
GMLANGatewayNotification -> VEHICLE_MOVEMENT_STATE
GMLANGatewayNotification -> VEHICLE_MOVEMENT_STATE
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