RGMII/RMII Converters (All are Ethernet Accessory only. Differs in Converters or Switch Ports)
rzn1_rgmii_rmii_conv_setup(conv_number, IF type, shoudRMIIrefclkOut?) {
1) CONVCTRL register setup → set static IF type and Clock output bits of CONVCTRL
set up of RGMII? or RMII? or MII? bit
if RMII, set CONVCTRL_REF_CLK_OUT bit
rzn1_rgmii_rmii_conv_speed(conv number, full_duplex?, speed?)→set dynamic speed and duplex bits of CONVCTRL
a) set 1000MBPS? 100MBPS? 10MBPS? speed bit (Only if not MII interface)
b) if full duplex, set FULL_DUPLEX bit
rzn1_rin_switchcore_setup() → Only switch ports (see the Converter-Switch port mapping below)
i) set 10M or/and 1000M bits of SWCTRL register according to speed.
ii) set the Duplex bit of SWDUPC register.
(It has been written in manual that these fields of SWCTRL and SWDUPC can be set to 0 and instead COMMAND_CONFIG_P[n] can used to set the actual values.)
2) reset using CONVRST register
clear PHYRST bit
wait for 1ms
set PHYRST bit
}
Ethernet Ports→Converters→PHYs→External Connectors. Consider, where and all PHY is coming there needs to be a converter. So, total 5 converters. One is GMAC1 directly exposed out and other four are for external ports of A5PSW switch.
Converter Mapping:
Converter 0 → Directly exposed GMAC1
(GMAC2<->Switch Port 4 is management port that does not have converter either)
Converter 1 → Switch Port 3
Converter 2 → Switch Port 2
Converter 3 → Switch Port 1
Converter 4 → Switch Port 0
The above converters are set as follows in U-boot
Converter 0 → RGMII, no RMII clock output
Converter 1 → RGMII, no RMII clock output (Switch Port 3)
Converter 2 → RGMII, no RMII clock output (Switch Port 2)
Converter 3 → MII, RMII clock output (Switch Port 1)
Converter 4 → MII, RMII clock output (Switch Port 0)
Now, come to actual A5PSW setting..
rzn1_switch_setup_port_speed(port, speed, eanble) {
1) rzn1_mt5pt_switch_setup_port_speed(port, speed)
if 1000M, set MBPS_1000 bit of MAC_CMD_CFGn(port) register
2) if (enable), rzn1_mt5pt_switch_enable_port(port)
set AUTH_PORT_AUTHORIZED bit of AUTH_PORT(port) register
set PORT_ENA_TXRX bit of PORT_ENA register
}
From Setup point of view,
First, set upstream port to fixed 1000M.
rzn1_switch_setup_port_speed(4, 1000M, 1);
Next, all other ports are setup by link-change callback (phy_adjust_link_notifier).
for (port = 0; port < 4; port++) {
rzn1_rgmii_rmii_conv_speed(4 - port, duplex, speed) → Dynamic link speed/duplex setting of CONVCTRL
rzn1_switch_setup_port_speed(port, speed, enable);
}
Regarding the PHY address assignment, if PHY address 4/5, it is MII. Otherwise, RGMII.
Look here, U-Boot just selects one external port from the switch, and based on the link speed/duplex of that specific port, it updates the same with all ports.
4.4 U-Boot Download and Reference source
4.4.1 Setup
On your host PC, the following command will download the RZ/N1 branch for U-Boot, including all
commit history. Note that it will result in a large download
git clone http://git.denx.de/u-boot.git
cd u-boot
Checkout a branch based on the 2017.01 version:
git checkout -b rzn1 v2017.01
Set the BSP version to according to the release, for example:
BSP_VERSION=v1.5.3
Fetch the RZ/N1 branch and merge it in:
git remote add renesas-rz https://github.com/renesas-rz/rzn1_u-boot.git
git fetch --tags renesas-rz
git merge rzn1-public-$BSP_VERSION
4.4.2 Build
To setup the configuration for the Renesas RZ/N1D-DB Board, run:
make rzn1d400-db_config
To setup the configuration for the Renesas RZ/N1S-DB Board, run:
make rzn1s324-db_config
To setup the configuration for the Renesas RZ/N1S IO-Link Board, run:
make rzn1s-io-link_config
To setup the configuration for the Renesas RZ/N1L-DB Board, run:
make rzn1l-db_config
To build U-Boot, run:
make
Once complete, the Elf image is stored as u-boot. The image is built to execute from internal
SRAM on the RZ/N1 devices, see section 5.2 for details. You can download this file using a
debugger.
By default, U-Boot uses the first available network interface. If that interface is down. It will try the
next one. You can set the default network interface to GMAC2, for example, by setting:
setenv ethact dwmac.44002000
