Cortex-R4 MPU setting

ARM Kernel Understanding

ARM Kernel Understanding:

You know that the IRQ handler saves the following Ten registers initially in the IRQ stack.

;    + 0|__U_sp__|
;    + 4|__U_lr__|
;    + 8|___r0___|
;    +12|___r1___|
;    +16|___r2___|
;    +20|___r3___|
;    +24|__dummy_| .. scratch(r0)
;    +28|__spsr__|
;    +32|__r12___|
;    +36|_lr(pc)_|

When this is first interrupt, all this registers are transferred to above the Task's stack (User SP) and the volatile registers of the context structure is formed. And, the User stack pointer is saved at the TCB of the task. This stack pointer is later acquired from the TCB of the task in the ret_int.

Since the mode is changed to the System mode at the end of ent_int, the ISP is assigned to the User stack pointer and further interrupt handler processing and further nested interrupt context saving is performed in the ISP. (Nested interrupt context saving is performed only in the IRQ stack, not ISP. ISP is only for the Interrupt handler processing)

The question remaining here is howmany registers are still remaining in the IRQ stack after transferring the stacked registers using ldfmd and how are they used?

When this is nested interrupt, the IRQ stack is not disturbed, but the VFP volatile registers too saved in the IRQ stack in case of VFP is enabled in the interrupt handler using ena_vpu() call. The ISP is used only for the Interrupt Handler processing.