Sleep mode in RZ/A1L

https://www.renesas.com/us/en/doc/products/mpumcu/tu/002/tnrza003ae.pdf

OMAPL137 to OMAPL138 migration

System Timer Interrupt
DDR Address
Interrupt Numbers

OMAP-L137 to OMAP-L138 Migration
http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/99134

ARM articles

Barrier instruction and Write buffer/Store buffer

https://www.aps-web.jp/academy/ca/11/

Cortex-R4: Difference between Normal and Device memory

Cortex™-R4 and Cortex-R4F Technical Reference Manual

Check the corresponding architecture's manual for "Write buffer", "Device memory" to know about the attributes more precisely.

--
Memory that is marked as Strongly-ordered or Device type is typically sensitive to the number
of reads or writes performed. Because of this, instructions that access Strongly-ordered or
Device memory are never abandoned when they have started accessing memory. These
instructions always complete either all or none of their memory accesses.
--
The processor memory system contains a store buffer that helps to improve the throughput of
accesses to Normal type memory. See Store buffer on page 8-18 for more information. Because
of the ordering rules that they must follow, accesses to other types of memory typically have a
lower throughput or higher latency than accesses to Normal memory. In particular:
• reads from Device memory must first drain the store buffer of all writes to Device memory
• all accesses to Strongly-ordered memory must first drain the store buffer completely.
Similarly, when it accesses Strongly-ordered or Device type memory, the processor's response
to interrupts must be modified, and the interrupt response latency is longer. See Low interrupt
latency on page 3-17 for more information.
To ensure optimum performance, you must understand the architectural semantics of the
different memory types. Use Device memory type for appropriate memory regions, typically
peripherals, and only use Strongly-ordered memory type for memory regions where it is
essential.
--
Store buffer merging
The store buffer has merging capabilities. If a previous write access has updated an entry, other
write accesses on the same line can merge into this entry. Merging is only possible for stores to
Normal memory.
Merging is possible between several entries that can be linked together if the data inside the
different entries belong to the same cache line.
No merging occurs for writes to Strongly-ordered or Device memory. The processor
automatically drains the store buffer as necessary, before performing Strongly-ordered accesses
or Device reads.
--
The store buffer is drained of all stores to Device memory before a load is performed from
Device memory.
--
Load and store instructions to Non-cacheable memory might not result in an AXI transfer
because the data might either be retrieved from, or merged into the internal store data buffers.
The exceptions to this are loads or stores to Strongly-ordered or Device memory. These always
result in AXI transfers.
--
A load or store instruction to or from Strongly-ordered or Device memory always generates AXI
transactions of the same size as implied by the instruction. All accesses using LDM, STM, LDRD, or
STRD instructions to Strongly-ordered or Device memory occur as 32-bit transfers.
--

Memory Region attribute

LPC54608 Could not debug

Regaining debug access to target MCU

https://community.nxp.com/thread/389112

ISP Reset over debug

https://community.nxp.com/thread/389040


ECRP setting examples
C:\Keil_v5\ARM\Pack\Keil\LPC54000_DFP\2.6.0\Device\Source\ARM\startup_LPC54608.s
C:\Keil_v5\ARM\Pack\Keil\LPC54000_DFP\2.6.0\Device\Source\IAR\startup_LPC54608.s


Debugger hang when running ttcp -t and ttcp -r simultaneously.
Increase the stack size of Rx and Tx tasks of ttcp program.

LPC54608 Ethernet Driver

https://www.oryx-embedded.com/doc/lpc54608__eth__driver_8c_source.html