Multicore

PowerPC timebase synchronization

http://www.tentech.ca/2010/09/easy-multi-core-powerpc-timebase-synchronization-with-simics/

L2 Cache during MultiCore

No L2 Cache at all - Neither CPU0 nor CPU1 enabled/disabled L2 Cache
CPU0 enable L2 Cache - CPU1 should not access at all. Initialization should not do disable/enable L2 access. Application programs not only access L2 cache, but L1 cache too. Because, the data is still cached in L2 cache.

Meaning of ACTLR.smp

https://community.arm.com/thread/3092

How to divide the L2 cache between the cores on a ARM Cortex-A7?

http://stackoverflow.com/questions/30612687/how-to-divide-the-l2-cache-between-the-cores-on-a-arm-cortex-a7

Coresight Debug Insights

https://community.arm.com/groups/processors/blog/2015/07/13/how-to-debug-coresight-basics-part-3