iOS Checkpoints

・Zero BSS section size

PL310

Invalidate:

Invalidate Line by PA - Specific L2 cache line is marked as not valid.

Clean:

Clean Line by PA Write the specific L2 cache line to L3 main memory if the line is marked as valid and dirty.
The line is marked as not dirty. The valid bit is unchanged.

Flush:

• For example, after a cache flush all lines are invalid.
• http://lxr.free-electrons.com/source/arch/arm/mm/cache-v7.S

 The data cache flush is now achieved using atomic clean / invalidates

ARM Recommended:

Invalidate All - Needed at Initailization
Invalidate a range - Example, network buffer reception by DMA buffer (Read only buffers)
Clean a range -
Flush a range () - Update change instructions in main memory and invalidate. Change in Instruction space (Write on unused domains)

Using ARM Caches

http://legup.eecg.utoronto.ca/wiki/doku.php?id=using_arm_caches


PL310 operations:


https://github.com/lentinj/u-boot/blob/master/arch/arm/lib/cache-pl310.c
http://lxr.free-electrons.com/source/arch/arm/mm/cache-l2x0.c


https://lxr.missinglinkelectronics.com/uboot/arch/arm/cpu/armv7/cache_v7.c

Porting DS-5/RDS/RVCT to GCC

Please refer to following `GNU ARM Assembler Quick Reference`
http://www.ic.unicamp.br/~celio/mc404-2014/docs/gnu-arm-directives.pdf